Abstract
For ultra-low power applications, steep sub-threshold slope transistors are promising candidate to replace the traditional MOSFETs. The limitations of Inter-Band Tunnel Field Effect Transistors (TFETs) due to unidirectional current conduction behaviour have been explored in this chapter for successful realization of compact SRAM bitcell for ultra-low supply voltages. Since, asymmetric current conduction in TFETs limits the viability of realization of 6T SRAM bitcells. A case study of 6T SRAM bitcell design using Si-TFETs for reliable operation with low leakage at ultra low voltages is presented. It is also demonstrated that a functional 6T TFET SRAM design with comparable stability margins and faster performances at low voltages can be realized using unidirectional TFETs devices when compared with the 7T TFET SRAM bitcell.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Bhuwalka, K., Sedlmaier, S., Ludsteck, A., Tolksdorf, C., Schulze, J., Eisele, I.: Vertical tunnel field-effect transistor. IEEE Trans. Electron Device 51(2), 279–282 (2004). doi:10.1109/TED.2003.821575
Chang, L., Nakamura, Y., Montoye, R., Sawada, J., Martin, A., Kinoshita, K., Gebara, F., Agarwal, K., Acharyya, D., Haensch, W., Hosokawa, K., Jamsek, D.: A 5.3 ghz 8T-SRAM with operation down to 0.41 v in 65 nm CMOS. In: IEEE Symposium on VLSI Circuits, 2007, Kyoto, pp. 252–253 (2007)
Chen, G.K., Blaauw, D., Mudge, T., Sylvester, D., Kim, N.S.: Yield-driven near-threshold SRAM design. In: ICCAD ’07: Proceedings of the 2007 IEEE/ACM International Conference on Computer-Aided Design, Lyon, pp. 660–666. IEEE Press, Piscataway (2007)
Fair, R., Wivell, H.: Zener and avalanche breakdown in As-implanted low-voltage Si n-p junctions. IEEE Trans. Electron Devices 23(5), 512–518 (1976)
Jiajing W., Nalam, S., Calhoun, B.H.: Analyzing static and dynamic write margin for nanometer SRAMs, ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 129–134 (2008) doi: 10.1145/1393921.1393954. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5529055&isnumber=5529013
Heald, R., Wang, P.: Variability in sub-100 nm SRAM designs. In: International Conference on Computer Aided Design, 2004. ICCAD-2004, San Jose, pp. 347–352 (2004)
Hurkx, G., Klaassen, D., Knuvers, M.: A new recombination model for device simulation including tunneling. IEEE Trans. Electron Devices 39(2), 331–338 (1992). doi:10.1109/16.121690
Ieong, M., Solomon, P., Laux, S., Wong, H.S., Chidambarrao, D.: Comparison of raised and schottky source/drain mosfets using a novel tunneling contact model. In: International Electron Devices Meeting, 1998. IEDM ’98 Technical Digest, pp. 733–736 (1998). doi:10.1109/IEDM.1998.746461
ITRS: International technology road map for semiconductors, test and test equipments. http://public.itrs.net/ (2006)
Khare, M., Ku, S., Donaton, R., Greco, S., Brodsky, C., Chen, X., Chou, A., DellaGuardia, R., Deshpande, S., Doris, B., Fung, S., Gabor, A., Gribelyuk, M., Holmes, S., Jamin, F., Lai, W., Lee, W., Li, Y., McFarland, P., Mo, R., Mittl, S., Narasimha, S., Nielsen, D., Purtell, R., Rausch, W., Sankaran, S., Snare, J., Tsou, L., Vayshenker, A., Wagner, T., Wehella-Gamage, D., Wu, E., Wu, S., Yan, W., Barth, E., Ferguson, R., Gilbert, P., Schepis, D., Sekiguchi, A., Goldblatt, R., Welser, J., Muller, K., Agnello, P.: A high performance 90 nm SOI technology with 0.992 m2 6T-SRAM cell. In: International Electron Devices Meeting, 2002. IEDM ’02. Digest, pp. 407–410 (2002). doi:10.1109/IEDM.2002.1175865
Kim, D., Lee, Y., Cai, J., Lauer, I., Chang, L., Koester, S.J., Sylvester, D., Blaauw, D.: Low power circuit design based on heterojunction tunneling transistors (HETTs). In: Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED ’09, pp. 219–224. ACM, New York (2009). doi:http://doi.acm.org/10.1145/1594233.1594287. http://doi.acm.org/10.1145/1594233.1594287
Lin, J., Toh, E., Shen, C., Sylvester, D., Heng, C., Samudra, G., Yeo, Y.: Compact HSPICE model for IMOS device. Electron. Lett. 44(2), 91–92 (2008). doi:10.1049/el:20083116
Meterelliyoz, M., Kulkarni, J.P., Roy, K.: Thermal analysis of 8-T SRAM for nano-scaled technologies. In: ISLPED ’08: Proceeding of the 13th International Symposium on Low Power Electronics and Design, pp. 123–128. ACM, New York (2008). doi:http://doi.acm.org/10.1145/1393921.1393953
Mookerjea, S., Datta, S.: Comparative study of si, ge and inas based steep subthreshold slope tunnel transistors for 0.25 v supply voltage logic applications. In: Device Research Conference, 2008, pp. 47–48 (2008). doi:10.1109/DRC.2008.4800730
Mookerjea, S., Krishnan, R., Datta, S., Narayanan, V.: On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors. IEEE, Electron Device Letters, 30(10), 1102–1104 (2009). doi:10.1109/LED.2009.2028907. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5232873&isnumber=5263237
PTM: Predictive technology model. In: Nanoscale Integration and Modeling (NIMO) Group. Arizona State University, Arizona. http://www.eas.asu.edu/ptm/ (2008)
Reddick, W.M., Amaratunga, G.A.J.: Silicon surface tunnel transistor. Appl. Phys. Lett. 67(4), 494–496 (1995). doi:10.1063/1.114547. http://link.aip.org/link/?APL/67/494/1
Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid-State Electron. 36(1), 19–34 (1993). doi:10.1016/0038--1101(93)90065-X. http://www.sciencedirect.com/science/article/B6TY5--46VC2XP-VV/2/4c4c69fef08ec975219a32ff521d55d6
Seevinck, E., List, F., Lohstroh, J.: Static-noise margin analysis of MOS SRAM cells. J. Solid-State Circuit 25(2), 784–754 (1987)
Sentaurus, S.: TCAD Sentaurus Device Manual, Release: Z-2007.03. Synopsys (2003)
Singh, J., Ramakrishnan, K., Mookerjea, S., Datta, S., Vijaykrishnan, N., Pradhan, D.: A novel Si-tunnel FET based SRAM design for ultra low-power 0.3 v vdd applications. In: Proceedings of the 2010 Asia and South Pacific Design Automation Conference, ASPDAC ’10, pp. 181–186. IEEE Press, Piscataway (2010). http://portal.acm.org/citation.cfm?id=1899721.1899761
Suzuki, T., Yamauchi, H., Yamagami, Y., Satomi, K., Akamatsu, H.: A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses. IEEE J. Solid-State Circuit 43(9), 2109–2119 (2008)
Sylvester, D.: Low power circuit design based on heterojunction tunneling transistors. In: Device Research Conference, Steep Slope or Slippery Slope, Rump Session, pp. 47–48 (2009). doi:10.1109/DRC.2008.4800730
Verma, N., Chandrakasan, A.P.: A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy. IEEE J. Solid-State Circuit 43(1), 141–149 (2008)
Wang, P.F.: Complementary tunneling FETs (CTFET) in CMOS technology. Ph.D. thesis, TU Munchen, Munich (2003). http://www.ece.udel.edu/~qli
Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N., Wang, Y., Zheng, B., Bohr, M.: A 3-ghz 70 mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply. In: IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC, 2005, vol. 1, pp. 474–611 (2005). http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1494075
Zhao, W., Cao, Y.: New generation of predictive technology model for sub-45 nm design exploration. In: ISQED ’06: Proceedings of the 7th International Symposium on Quality Electronic Design, pp. 585–590. IEEE Computer Society, Washington (2006). doi:http://dx.doi.org/10.1109/ISQED.2006.91
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Singh, J., Mohanty, S.P., Pradhan, D.K. (2013). SRAM Bitcell Design Using Unidirectional Devices. In: Robust SRAM Designs and Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0818-5_5
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0818-5_5
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-0817-8
Online ISBN: 978-1-4614-0818-5
eBook Packages: EngineeringEngineering (R0)