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2-Port SRAM Bitcell Design

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Robust SRAM Designs and Analysis

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Abstract

A low power, minimum transistor count and fast access Static Random Access Memories (SRAMs) are essential for embedded multimedia and communication applications realized using System-on-Chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems to enhance the memory bandwidth. In this chapter, multi-port SRAM bitcells are studied and their merits and de-merits are highlighted. A case study of 2-port six transistors (6T) SRAM bitcell with multi-port capabilities at reduced area overhead as compared to existing 2-port 7T and 8T SRAM bitcells, is also presented. A major challenge in designing the multi-port SRAM bitcells is maintaining the simultaneous read and write access without hampering the stability of neighbouring bitcells is a prime concern for which an array organization is also discussed which eliminates the partial write disturbance. Re-configuration of separate read-port of 7T SRAM bitcell reduces the bitline leakage current and makes the bitline sensing more robust and avoids the erroneous read operation caused due to false pull-down of the bitline. The process variation sensitivity analysis of different SRAM bitcells is also discussed to identify which SRAM transistor is in lead role to minimize the process variation effect.

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Authors and Affiliations

  1. Indian Institute of Information Technology Design and Manufacturing, Dumna Airport Road, Jabalpur, India

    Jawar Singh

  2. University of North Texas, Discovery Park, 3940 N. Elm, Room F247, Denton, USA

    Saraju P. Mohanty

  3. University of Bristol, Merchant Venturers Building Woodland Rd., Bristol, UK

    Dhiraj K. Pradhan

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  1. Jawar Singh
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  2. Saraju P. Mohanty
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  3. Dhiraj K. Pradhan
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Singh, J., Mohanty, S.P., Pradhan, D.K. (2013). 2-Port SRAM Bitcell Design. In: Robust SRAM Designs and Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0818-5_4

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  • DOI: https://doi.org/10.1007/978-1-4614-0818-5_4

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