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Introduction to SRAM

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Robust SRAM Designs and Analysis

Abstract

The trend of Static Random Access Memory (SRAM) along with CMOS technology scaling in different processors and system-on-chip (SoC) products has fuelled the need of innovation in the area of SRAM design. SRAM bitcells are made of minimum geometry devices for high density and to keep the pace with CMOS technology scaling, as a result, they are the first to suffer from technology scaling induced side-effects. At the same time, success of next generation technology depends on the successful realization of SRAM. Therefore, different SRAM bitcell topologies and array architectures have been proposed in the recent past to meet the nano-regime challenges. Some of the major challenges in SRAM design includes poor stability, process variation tolerance, device degradation due to ageing and soft errors. In this chapter, introduction and importance of SRAM in memory hierarchy of a modern computer system and its peripheral circuitries have been presented. Different SRAM bitcell topologies and their merits and de-merits are also highlighted.

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Authors and Affiliations

  1. Indian Institute of Information Technology Design and Manufacturing, Dumna Airport Road, Jabalpur, India

    Jawar Singh

  2. University of North Texas, Discovery Park, 3940 N. Elm, Room F247, Denton, USA

    Saraju P. Mohanty

  3. University of Bristol, Merchant Venturers Building Woodland Rd., Bristol, UK

    Dhiraj K. Pradhan

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  1. Jawar Singh
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  2. Saraju P. Mohanty
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  3. Dhiraj K. Pradhan
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Singh, J., Mohanty, S.P., Pradhan, D.K. (2013). Introduction to SRAM. In: Robust SRAM Designs and Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0818-5_1

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  • DOI: https://doi.org/10.1007/978-1-4614-0818-5_1

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