Abstract
A simple method of keeping devices turned off is proposed in addition to low-voltage technology such as sub-1-V technology. That is we need to keep devices in a turned-off state as long as possible when not in use, but we need to turn them on instantly when they are required to perform optimally [1, 2]. We usually do this in daily situations as we are faced by increasing concerns with limited resources, but we also do it for greater efficiency. However, it is not easy to apply this concept to actual IT equipment. Although practical instant ON and OFF functions should be implemented in this approach, they require fundamental revisions to the computing architecture. This predicament also raises the need for an approach to combine power-control and computing technologies (information processing technology), to form a basic technology that will generate social innovation in our daily lives.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Kawahara T, Ito K, Takemura R, Ohno H (2012) Spin-transfer torque RAM technology: review and prospect. Microelectron Reliab (ELSEVIER) 52(4):613–627
Kawahara T (2011) Scalable spin-transfer torque RAM technology for normally-off computing. IEEE Des Test Comput 28(1):52–63
Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K, Yamada H, Shoji M, Hachino H, Fukumoto C, Nagao H, Kano H (2005) A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. International electron devices meeting (iedm), 2005, pp 459–462
Kawahara T, Takemura R, Miura K, Hayakawa J, Ikeda S, Lee Y, Sasaki R, Goto Y, Ito K, Meguro T, Matsukura F, Takahashi H, Matsuoka H, Ohno H (2007) 2 Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. International solid-state circuits conference (ISSCC), 2007, pp 480–481
Tsuchida K, Inaba T, Fujita K, Ueda Y, Shimizu T, Asao Y, Kajiyama T, Iwayama M, Sugiura K, Ikegawa S, Kishi T, Kai T, Amano M, Shimomura N, Yoda H, Watanabe Y (2010) A 64 Mb MRAM with clamped-reference and adequate-reference schemes. International solid-state circuits conference (ISSCC), 2010, pp 258–259
Chung S, Rho KM, Kim SD, Suh HJ, Kim DJ, Kim HJ, Lee SH, Park JH, Hwang HM, Hwang SM, Lee JY, An YB, Yi JU, Seo YH, Jung DH, Lee MS, Cho SH, Kim JN, Park GJ, Jin G, Driskill-Smith A, Nikitin V, Ong A, Tang X, Kim Y, Rho JS, Park SK, Chung SW, Jeong JG, Hong SJ (2010) Fully integrated 54 nm STT-RAM with the smallest bit cell dimension for high density memory application. International electron devices meeting (iedm), 2010, pp 12.7.1–12.7.4
Ohno H, Endoh T, Hanyu T, Kasai N, Ikeda S (2010) Magnetic tunnel junction for nonvolatile CMOS logic. Technical digest, International electron devices meeting 2010 (IEDM2010), pp 9.4.1–9.4.4, Dec 2010
Matsunaga S, Hayakawa J, Ikeda S, Miura K, Hasegawa H, Endoh T, Ohno H, Hanyu T (2008) Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions. Appl Phys Express 1:091301
Matsunaga S, Hiyama K, Matsumoto A, Ikeda S, Hasegawa H, Miura K, Hayakawa J, Endoh T, Ohno H, Hanyu T (2009) Standby-power-free compact ternary content-addressable memory cell chip using magnetic tunnel junction devices. Appl Phys Express 2:023004 (3 pages)
Suzuki D, Natsui M, Ikeda S, Hasegawa H, Miura K, Hayakawa J, Endoh T, Ohno H, Hanyu T (2009) Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array. In: IEEE 2009 symposium on VLSI circuits digest of technical papers, pp 80–81
Aoki H, Kawahara T, Yamaoka M, Yoshimura C, Nagasaka Y, Takayama K, Sukegawa N, Fukumura Y, Nakahata M, Sawamoto H, Odaka M, Sakurai T, Kasai K (2008) A powerful yet ecological parallel processing system using execution-based adaptive power-down adaptive power-down control and compact quadruple-precision assist FPUs. In: IEEE symposium on VLSI circuits, pp 186–187
Katayama Y, Stuckey EJ, Morioka S, Wu Z (1999) Fault-tolerant refresh power reduction DRAMs for quasi-nonvolatile data retention. In: International symposium on defect and fault tolerance in VLSI systems (DFT ‘99), pp 311–318
Acknowledgments
This work was supported in part by the “High-Performance Low-Power Consumption Spin Devices and Storage Systems” program (headed by Professor Hideo Ohno of Tohoku University) under Research and Development for the Next-Generation Information Technology of the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), and also by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program). The authors wish to thank the conscientious contributors to spin-transfer torque RAM (SPRAM) technology at Hitachi and Tohoku University for their support.
This work was also supported in part by a project on “Fundamental Technologies for Next Generation Supercomputing” made available by the Japanese government’s MEXT.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Kawahara, T., Yoshimura, C. (2013). Low Power Processing with NV-RAM. In: Kawahara, T., Mizuno, H. (eds) Green Computing with Emerging Memory. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0812-3_8
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0812-3_8
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-0811-6
Online ISBN: 978-1-4614-0812-3
eBook Packages: EnergyEnergy (R0)