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Low-Power NV-RAM

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Green Computing with Emerging Memory

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Abstract

Memories are key devices in information communication equipment such as servers, network routers, switches, and mobile devices to improve their functions and performance. Conventional memories can be categorized into two groups. One is known as random access memory (RAM), for example, static RAM (SRAM) and dynamic RAM (DRAM). These RAMs are volatile, but they have advantageous features including infinite write cycles and fast read and write operations. Therefore, they are suitable for the main memory of electrical equipment. The other category is read-only memory (ROM). ROM is used to store data and/or source code of systems. Several kinds of memory technologies for ROM exist. The most common ROM is Flash memory. A NAND-type Flash memory is the densest kind of semiconductor memory and is now being used as the storage device in small form factor hard disk drives (HDDs).

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References

  1. Boech JD, Borghs G (1999) Magnetoelectronic devices, in IEEE international electron devices meeting, Dig technical papers, pp 215–218, Dec 1999

    Google Scholar 

  2. Lai S, Lowery T (2001) OUM—a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications, in IEEE international electron devices meeting, Dig technical papers, pp 803–806, Dec 2001

    Google Scholar 

  3. Zhuang WW, Pan W, Ulrich BD, Lee JJ, Stecker L, Burmaster A, Evans DR, Hsu ST, Tajiri M, Shimaoka A, Inoue K, Naka T, Awaya N, Saiyam A, Yang Y, Liu SQ, Wu NJ, Ignatiev A (2002) Novell colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM). In: IEEE international electron devices meeting, Dig technical papers, pp 193–196, Dec 2002

    Google Scholar 

  4. Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K, Yamada H, Shoji M, Hachinoa H, Fukumoto C, Nagao H, Kano H (2005) A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In: IEEE international electron devices meeting, Dig technical papers, pp 459–462, Dec 2005

    Google Scholar 

  5. Matsuzaki N, Kurotsuchi K, Matsui Y, Tonomura O, Yamamoto N, Fujisaki Y, Kitai N, Takemura R, Osada K, Hanzawa S, Moriya H, Iwasaki T, Kawahara T, Takaura N, Terao M, Matsuoka M, Moniwa M (2005) Oxygen-doped GeSbTe phase-change memory cells featuring 1.5-V/100-μA standard 0.13-μm CMOS operations. In: IEEE international electron devices meeting, Dig technical papers, pp 757–760, Dec 2005

    Google Scholar 

  6. Villa C, Mills D, Barkley G, Giduturi H, Schippers S, Vimercati D (2005) A 45 nm 1 Gb 1.8 V phase-change memory. In: IEEE international solid-state circuits conference. Dig technical papers, pp 270–271, Feb 2005

    Google Scholar 

  7. Lee K-J, Cho B-H, Cho W-Y, Kang S, Choi B-G, Oh H-R, Lee C-S, Kim H-J, Park J-M, Wang Q, Park M-H, Ro Y-H, Choi J-Y, Kim K-S, Kim Y-R, Shin I-C, Lim K-W, Cho H-K, Choi C-H, Chung W-R, Kim D-E, Yu K-S, Jeong G-T, Jeong H-S, Kwak C-K, Kim C-H, Kim K (2007) A 90 nm 1.8 V 512 Mb Diode-switch PRAM with 266 MB/s read throughput. In: IEEE international solid-state circuits conference, Dig technical papers, pp 474–473, Feb 2007

    Google Scholar 

  8. Chung H, Jeong BH, Min BJ, Choi Y, Cho B-H, Shin J, Kim J, Sunwoo J, Park J-M, Wang Q, Lee Y-J, Cha S, Kwon D, Kim S, Kim S, Rho Y, Park M-H, Kim J, Song I, Jun S, Lee J, Kim KS, Lim K-W, Chung W-R, Choi CH, Cho HG, Shin I, Jun W, Hwang S, Song K-W, Lee KJ, Chang S-W, Cho W-Y, Yoo J-H, Jun Y-H (2011) A 58 nm 1.8 V 1 Gb PRAM with 6.4 MB/s program BW. In: IEEE international solid-state circuits conference, Dig technical papers, pp 500–501, Feb 2011

    Google Scholar 

  9. Sawa A, Fujii T, Kawasaki M, Tokura Y (2004) Hysteretic current-voltage characteristics and resistance switching at a rectifying Ti/Pr0.7Ca0.3MnO3 interface. Appl Phys Lett 85(18):4073–4075

    Article  Google Scholar 

  10. Sim HJ, Choi HJ, Lee DS, Chang M, Choi DH, Son U, Lee E-H, Kim WJ, Park UD, Yoo I-K, Hwang HS (2005) Excellent resistance switching characteristics of Pt/SrTiO3 Schottky junction for multi-bit nonvolatile memory application. In: IEEE international electron devices meeting, Dig technical papers, pp 758–761, Dec 2005

    Google Scholar 

  11. Ono K, Kurotsuchi K, Fujisaki Y, Takemura R, Terao M, Takaura N (2009) Resistive switching. ion-plug memory for. 32-nm technology. Node and Beyond. Jpn J Appl Phys 48:04C160

    Google Scholar 

  12. Chevallier CJ, Siau CH, Lim SF, Namala SR, Matsuoka M, Bateman BL, Rinerson D, (2010) A 0.13 μm 64 Mb multi-layered conductive metal-oxide memory. In: IEEE international solid-state circuits conference, Dig technical papers, pp 260–261, Feb 2010

    Google Scholar 

  13. Wu Y, Chai Y, Chen H-Y, Yu S, Philip Wong H–S (2011) Resistive switching AlOx-based memory with CNT electrode for ultra-low switching current and high density memory application. In: Symposium on VLSI technology, Dig technical papers, pp 26–27, June 2011

    Google Scholar 

  14. Durlam M, Naji P, DeHerrera M, Tehrani S, Kerszykowski G, Kyler K (2000) Nonvolatile RAM based on magnetic tunnel junction elements. In: IEEE international solid-state circuits conference, Dig technical papers, pp 130–131, Feb 2000

    Google Scholar 

  15. Scheuerlein R, Gallagher W, Parkin S, Lee A, Ray S, Robertazzi R, Reohr W (2000) A 10 ns read and write non-volatile memory array using a magnetic tunnel junction and FET switch in each cell. In: IEEE international solid-state circuits conference, Dig technical papers, pp 128–129, Feb 2000

    Google Scholar 

  16. Naji PK, Durlam M, Tehrani S, Calder J, DeHerrera MF (2001) A 256 kb 3.0 V 1T1MTJ nonvolatile magnetoresistive RAM. In: IEEE international solid-state circuits conference, Dig technical papers, pp 122–123, Feb 2001

    Google Scholar 

  17. Durlam M, Naji P, Omair A, DeHerrera M, Calder J, Slaughter JM, Engel B, Rizzo N, Grynkewich G, Butcher B, Tracy C, Smith K, Kyler K, Ren J, Molla J, Feil B, Williams R, Tehrani S (2002) A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects. In: Symposium on VLSI circuits, Dig technical papers, pp 158–161, June 2002

    Google Scholar 

  18. Nahas J, Andre T, Subramanian C, Garni B, Lin H, Omair A, Martino W (2004) A 4 Mb 0.18 μm 1T1MTJ Toggle MRAM memory. In: IEEE international solid-state circuits conference, Dig technical papers, pp 44–45, Feb 2004

    Google Scholar 

  19. DeBrosse J, Amdt C, Banvin C, Bette A, Gogl D, Gowl E, Hoenigschmid H, Lammers S, Lamoreyl M, Lu Y, Maffitt T, Maloney K, Obermeye W, Sturn A, Viehmann H, Willmottl D, Wood M, Gallagher WJ, Mueller G, Sitaram AR (2004) A 16 Mb MRAM featuring bootstrapped write drivers. In: Symposium on VLSI circuits, Dig technical papers, pp 454–457 June 2004

    Google Scholar 

  20. Hosomi M, Yamagishi H, Yamamoto T, Bessho K, Higo Y, Yamane K, Yamada H, Shoji M, Hachinoa H, Fukumoto C, Nagao H, Kano H (2005) A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In: IEEE international electron devices meeting, Dig technical papers, pp 459–462, Dec 2005

    Google Scholar 

  21. Kawahara T, Takemura R, Miura K, Hayakawa J, Ikeda S, Lee YM, Sasaki R, Goto Y, Ito K, Meguro T, Matsukura F, Takahashi H, Matsuoka H, Ohno H (2008) 2 Mb SPRAM (SPin-transfer torque RAM) with bit-by-bit bi-directional current write and parallelizing-direction current read. IEEE J Solid-State Circ 43(1):109–120

    Article  Google Scholar 

  22. Takemura R, Kawahara T, Miura K, Yamamoto H, Hayakawa J, Matsuzaki N, Ono K, Yamanouchi M, Ito K, Takahashi H, Ikeda S, Hasegawa H, Matsuoka H, Ohno H (2009) 32-Mb 2T1R SPRAM with localized bi-directional write driver and “1”/”0” dual-array equalized reference cell. In: Symposium VLSI circuit, Dig technical papers, pp 84–85

    Google Scholar 

  23. Tsuchida K, Inaba T, Fujita K, Ueda Y, Shimizu T, Asao Y, Kajiyama T, Iwayama M, Sugiura K, Ikegawa S, Kishi T, Kai T, Amano M, Shimomura N, Yoda H, Watanabe Y (2011) A 64 Mb MRAM with Clamped-reference and adequate-reference schemes. In: IEEE international solid-state circuits conference, Dig technical papers, pp 258–259, Feb 2011

    Google Scholar 

  24. Miura K, Kawahara T, Takemura R, Hayakawa J, Ikeda S, Sasaki R, Takahashi H, Matsuoka H, Ohno H (2007) A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion. In: Symposium on VLSI technology, Dig technical papers, pp 234–235, June 2007

    Google Scholar 

  25. Li Z, Zhang S (2004) Thermally assisted magnetization reversal in the presence of a spin-transfer torque. Phys Rev B 69(13):134416

    Google Scholar 

  26. Takemura R, Kawahara T, Ono K, Miura K, Matsuoka H, Ohno H (2011) Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond. Solid-State Electronics 58(1):28–33

    Article  Google Scholar 

  27. Takemura R, Kawahara T, Hayakawa J, Miura K, Ito K, Yamanouchi M, Ikeda S, Takahashi H, Matsuoka H, Ohno H (2008) TMR Design methodology for SPin-transfer torque RAM (SPRAM) with nonvolatile and SRAM compatible operations. In: Non-Volatile semiconductor memory workshop 2008, and 2008 international conference on memory technology and design. NVSMW/ICMTD 2008, pp 54–55

    Google Scholar 

  28. Song K-W, Kim J-Y, Yoon J-M, Kim S, Kim H, Chung H-W, Kim H, Kim K, Park H-W, Kang HC, Tak N-K, Park D, Kim W-S, Lee Y-T, Oh YC, Jin G-Y, Yoo J, Park D, Oh K, Kim C, Jun Y-H (2010) A 31 ns random cycle VCAT-Based 4F2 DRAM with manufacturability and enhanced cell efficiency. IEEE J Solid-State Circ 45(4):880–888

    Article  Google Scholar 

  29. Yoshida C, Kurasawa M, Min Lee Y, Tsunoda K, Aoki M, Sugiyama Y (2009) A study of dielectric break-down mechanism in CoFeB/MgO/CoFeB magnetic tunnel junction. IEEE international reliability physics symposium, pp 139–142

    Google Scholar 

  30. Hosotani K, Asao Y, Nagamine M, Ueda T, Aikawa H, Shimomura N, Ikegawa S, Kajiyama T, Takahashi S, Nitayama A, Yoda H (2007) Effect of interface buffer layer on the reliability of Ultra-Thin MgO magnetic tunnel junctions for Spin transfer switching MRAM. IEEE international reliability physics symposium, pp 650–651

    Google Scholar 

  31. Nakamura M, Takahashi T, Akiba T, Kitsukawa G, Sekiguchi T, Asano I, Komatsuzaki K, Tadaki Y, Cho SS, Kajigaya K, Tachibana T, Sato K (1996) A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J Solid-State Circ 31(9):1302–1307

    Article  Google Scholar 

  32. Song K-W, Kim J-Y, Yoon J-M, Kim S, Kim H, Chung H-W, Kim H, Kim K, Park H-W, Kang HC, Tak N-K, Park D, Kim W-S, Lee Y-T, Oh YC, Jin G-Y, Yoo J, Park D, Oh K, Kim C, Jun Y-H (2010) A 31 ns random cycle VCAT-Based 4F2 DRAM with manufacturability and enhanced cell efficiency. IEEE J Solid-State Circ 45(4):880–888

    Article  Google Scholar 

  33. Endoh T, Hanyu T (2009) Impact of spintronic devices for future nano silicon base LSI. In: 5th international school and conference on spintronics and quantum information techinology(SPINTECH V ), Cracow, Poland, July 2009

    Google Scholar 

  34. Ono K, Kawahara T, Takemura R, Miura K, Yamamoto H, Yamanouchi M, Hayakawa J, Ito K, Taka-hashi H, Ikeda S, Hasegawa H, Matsuoka H, Ohno H (2009) A disturbance-free read scheme and a compact stochastic-spin-dynamics-based MTJ circuit model for Gb-scale SPRAM. IEEE international electron devices meeting (iedm), pp 9.3.1–9.3.4

    Google Scholar 

  35. Ishigaki T, Kawahara T, Takemura R, Ono K, Ito K, Matsuoka H, Ohno H (2010) A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions. In: Symposium on VLSI technology, Dig technical papers, pp 47–48, June 2010

    Google Scholar 

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Acknowledgments

This work was supported in part by the “High-Performance Low-Power Consumption Spin Devices and Storage Systems” program (headed by Professor Hideo Ohno of Tohoku University) under Research and Development for Next-Generation Information Technology of MEXT, and also by the Japan Society for the Promotion of Science (JSPS) through its “Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program). The authors sincerely thank the energetic people who have contributed to the development of STT-RAM technology at Hitachi and at Tohoku University.

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  1. Central Research Laboratory, Hitachi Ltd, Tokyo, Japan

    Riichiro Takemura

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  1. Riichiro Takemura
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Correspondence to Riichiro Takemura .

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  1. Hitachi Ltd, Chief Researhcer, Life Science Research, Tokyo, Japan

    Takayuki Kawahara

  2. , Hitachi Ltd, Central Research Laboratory, 1-280 Higashi-Koigakubo Kokubunji, Tokyo, 185-8601, Japan

    Hiroyuki Mizuno

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Takemura, R. (2013). Low-Power NV-RAM. In: Kawahara, T., Mizuno, H. (eds) Green Computing with Emerging Memory. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0812-3_6

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  • DOI: https://doi.org/10.1007/978-1-4614-0812-3_6

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