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Low-Power SRAM

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Green Computing with Emerging Memory

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Abstract

Today, SRAM is an indispensable device in SoCs. The SRAM is used in processor LSIs as an embedded memory because SRAM has manufacturing process compatibility and performance compatibility to the logic circuits, which are used in processor LSIs to process the data. When manufacturing the LSIs such as processors, the SRAM can be integrated in the LSIs without additional process cost. SRAM also has a low latency and random-accessible features. These features are important to use the SRAM as cache memory modules in processors.

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References

  1. Warnock J, Chan Y, Huott W, Carey S, Fee M, Wen H, Saccamango MJ, Malgioglio F, Meaney P, Plass D, Chan Y-H, Mayo M, Mayer G, Sigal L, Rude D, Averill R, Wood M, Strach T, Smith H, Curran B, Schwarz E, Eisen L, Malone D, Weitzel S, Mak P-K, McPherson T, Webb C (2011) A 5.2 GHz microprocessor chip for the IBM zEnterprise System. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 70–71

    Google Scholar 

  2. Fischer T, Arekapudi S, Busta E, Dietz C, Golden M, Hilker S, Horiuchi A, Hurd KA, Johnson D, McIntyre H, Naffziger S, Vinh J, White J, Wilcox K (2011) Design solutions for the Bulldozer 32 nm SOI 2-Core Processor Module in an 8-Core CPU. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 78–79

    Google Scholar 

  3. Riedlinger RJ, Bhatia R, Biro L, Bowhill B, Fetzer E, Gronowski P, Grutkowski T (2011) A 32 nm 3.1 billion transistor 12-wide-issue itanium processor for mission-critical servers. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 84–85

    Google Scholar 

  4. Uetake T et al (1999) A 1.0 ns Access 770 MHz 36 Kb SRAM Macro. In: Symposium on VLSI circuits digest of technical papers, pp 109–110

    Google Scholar 

  5. Osada K, Shin JL, Khan M, Liou Y, Wang K, Shoji K, Kuroda K, Ikeda S, Ishibashi K (2001) Universal-Vdd 0.65–2.0-V 32-kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell. IEEE J Solid-State Circuits 36(11):1738–1744

    Article  Google Scholar 

  6. Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circuits SC-22(5):748–754

    Google Scholar 

  7. Yamaoka M, Osada K, Ishibashi K (2002) 0.4-V Logic-library-friendly SRAM array using rectangular-diffusion cell and delata-boosted array voltage scheme. In: Symposium on VLSI circuits digest of technical papers, pp 170–173

    Google Scholar 

  8. Hisamoto Digh, Lee Wen-Chin, Kedzierski Jakub, Takeuchi Hideki, Asano Kazuya, Kuo Charles, Anderson Erik, King Tsu-Jae, Bokor Jeffrey, Chenming HU (2000) FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47:2320–2325

    Article  Google Scholar 

  9. Nackaerts A, Ercken M, Demuynck S, Lauwers A, Baerts C, Bender H, Boulaert W, Collaert N, Degroote B, Delvaux C, de Marneffe JF, Dixit A, De Meyer K, Hendrickx E, Heylen N, Jaenen P, Laidler D, Locorotondo S, Maenhoudt M, Moelants M, Pollentier I, Ronse K, Rooyackers R, Van Aelst J, Vandenberghe G, Vandervorst W, Vandeweyer T, Vanhaelemeersch S, Van Hove M, Van Olmen J, Verhaegen S, Versluijs J, Vrancken C, Wiaux V, Jurczak M, Biesemans S (2004) A 0.314μm2 6T-SRAM cell build with tall triple-gate devices for 45 nm node applications using 0.75NA 193 nm lithography. In: IEEE international electron devices meeting 2004 (IEDM technical digest), pp 269–272

    Google Scholar 

  10. Kawasaki H, Okano K, Kaneko A, Yagishita A, Izumida T, Kanemura T, Kasai K, Ishida T, Sasaki T, Takeyama Y, Aoki N, Ohtsuka N, Suguro K, Eguchi K, Tsunashima Y, Inaba S, Ishimaru K, Ishiuchi H (2006) Embedded Bulk FinFET SRAM cell technology with Planar FET peripheral circuit for hp32 nm node and beyond. In: IEEE Symposium on VLSI technology digest of technical papers., pp 70–71

    Google Scholar 

  11. Pelgrom MJ, Duinmaijar ACJ (1989) Matching properties of MOS transistors. IEEE J Solid-State Circuits 24(5):1433–1440

    Article  Google Scholar 

  12. Stolk PA et al (1998) Modeling statistical dopant fluctuations in MOS transistors. IEEE Trans Electron Devices 45(9):1960–1971

    Article  Google Scholar 

  13. Yamaoka M, Maeda N, Shinozaki Y, Shimazaki Y, Nii K, Shimada S, Yanagisawa K, Kawahara T (2005) Low-power embedded SRAM modules with expanded margins for writing. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 480–481

    Google Scholar 

  14. Tsukamoto Y, Nii K, Imaoka S, Oda Y, Ohbayashi S, Yoshizawa T, Makino H, Ishibashi K, Shinohara H (2005) Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-Array with local vth variability. In: Proceedings of ICCAD, pp 394–405

    Google Scholar 

  15. Zhang K et al (2005) A 3-GHz 70 Mb SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply. In: Proceedings of digest of technical papers. In: IEEE international solid-state circuits conference ISSCC, pp 474–475

    Google Scholar 

  16. Khellah M et al (2006) A 4.2 GHz 0,3mm2 256 kb Dual-Vcc SRAM building block in 65 nm CMOS. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 624–625

    Google Scholar 

  17. Pille J et al (2007) Implementation of the CELL Broadband EngineTM in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 322–323

    Google Scholar 

  18. Yamaoka M et al (2008) A 65 nm low-power high-density SRAM operable at 1.0 V under 3sigma systematic variation using separate Vth monitoring and body bias for NMOS and PMOS. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 382–383

    Google Scholar 

  19. Pilo H, Arsovski I, Batson K, Braceras G, Gabric J, Houle R, Lamphier S, Pavlik F, Seferagic A, Chen LY, Ko SB, Radens C (2011) A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI technology with 0.7 V operation enabled by stability, write-ability and read-ability enhancements. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 254–255

    Google Scholar 

  20. Morita Y, Fujiwara H, Noguchi H, Iguchi Y, Nii K, Kawaguchi H, Yoshimoto M (2007 An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment. In: Symposium on VLSI circuits digest of technical papers, pp 256–257

    Google Scholar 

  21. Takeda K, Hagihara Y, Aimoto Y, Nomura M, Nakazawa Y, Ishii T, Kobatake H (2006) A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J Solid-State Circuits 41(1):113–121

    Article  Google Scholar 

  22. Chang IJ et al (2008) A 32 kb 10T subthreshold SRAM Array with bit-interleaving and differential read scheme in 90 nm CMOS. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 388–389

    Google Scholar 

  23. Osada K, Saito Y, Ibe E, Ishibashi K (2003) 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J Solid-State Circuits 38(11):1952–1957

    Article  Google Scholar 

  24. Tega N, Miki H, Yamaoka M, Kume H, Mine T, Ishida T, Mori Y, Yamada R (2008) Torii impact of threshold voltage fluctuation due to random telegraph noise on scaled-down. In: IEEE international reliability physics symposium IRPS technical papers, pp.541–544

    Google Scholar 

  25. Yamaoka M, Miki H, Bansal A, Wu S, Frank DJ, Leobandung E, Torii K (2011) Evaluation methodology for random telegraph noise effects in SRAM Arrays. In: Proceedings of IEEE IEDM technical digest paper, pp 745–748

    Google Scholar 

  26. Yamaoka M, Shinozaki Y, Maeda N, Shimazaki Y, Kato K, Shimada S, Yanagisawa K, Osada K (2005) A 300-MHz 25-uA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J Solid-State Circuits 40(1):186–194

    Article  Google Scholar 

  27. Romanovsky S et al (2008) A 500 MHz random-access embedded 1 Mb DRAM Macro in Bulk CMOS. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 270–271

    Google Scholar 

  28. Singh et al (A) A 2 ns-Read-Latency 4 Mb Em-bedded floating-body memory macro in 45 nm SOI technology. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 460–461

    Google Scholar 

  29. Hanzawa S et al (2007) A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 474–475

    Google Scholar 

  30. Kawahara T et al (2007) 2 Mb Spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 480–481

    Google Scholar 

  31. Shiga et al H (2009) A 1.6 GB/s DDR2 128 Mb chain FeRAM with scalable octal bitline and sensing schemes. In: Proceedings of digest of technical papers. IEEE international solid-state circuits conference ISSCC, pp 464–465

    Google Scholar 

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Authors and Affiliations

  1. Central Research Laboratory, Hitachi Ltd, Tokyo, Japan

    Masanao Yamaoka

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  1. Masanao Yamaoka
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Correspondence to Masanao Yamaoka .

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Editors and Affiliations

  1. Hitachi Ltd, Chief Researhcer, Life Science Research, Tokyo, Japan

    Takayuki Kawahara

  2. , Hitachi Ltd, Central Research Laboratory, 1-280 Higashi-Koigakubo Kokubunji, Tokyo, 185-8601, Japan

    Hiroyuki Mizuno

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Yamaoka, M. (2013). Low-Power SRAM. In: Kawahara, T., Mizuno, H. (eds) Green Computing with Emerging Memory. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0812-3_4

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  • DOI: https://doi.org/10.1007/978-1-4614-0812-3_4

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  • Print ISBN: 978-1-4614-0811-6

  • Online ISBN: 978-1-4614-0812-3

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