Error Location and Reconfiguration

Abstract

This is the second and the last chapter of this book devoted to on-line Network-on-Chip (NoC) testing strategies. As mentioned before, the main difference of on-line and off-line tests is that the former detects run-time faults during system’s mission mode, while in the latter is typically used to detect manufacturing defects while the system is in test mode. Compared to the previous chapter, this one presents techniques used at the router, NoC, and system levels, while the previous chapter focuses on link and router level techniques. The most used techniques at the router, NoC, and the system levels are fault tolerant and adaptive routing algorithms – where an alternative path is found, avoiding the defective part of the NoC – and fault reconfiguration – where the hardware or the software are reconfigured to mask and isolate the defective block. However, both techniques assume they are able to pinpoint the exact location of a hardware defect. This task alone, called fault location, can be a challenge itself, since NoCs are scalable and they can have hundreds or even thousands of switching elements. Similarly to the previous chapter, the test approaches presented in this chapter also have costs in terms of, for instance, silicon area, network performance, network congestion, and energy consumption. Thus, the challenge for the designer is, again, to find a good trade-off between these costs and the potential benefit of the test approach in terms of reliability. However, this trade-off evaluation is typically much more complex at the NoC level than it is at link or router level, due to the size of NoCs and complex data communication patterns of the applications. This chapter presents the most relevant on-line NoC testing strategies at the NoC and system levels and their results in terms of costs and reliability.