Abstract
This part of the book is devoted to on-line Network-on-Chip (NoC) testing strategies, while the previous part is devoted to off-line NoC testing strategies. The main difference is that the former detects run-time faults during system’s mission mode, while in the latter is typically used to detect manufacturing defects while the system is in test mode. This chapter is devoted to on-line fault detection on data transmitted over the NoC. Due to the effect of deep submicron (DSM) technologies on the circuit reliability, the designer can no longer assume that the NoC is fault free during its normal execution. This way, designers add test approaches such as error control coding (ECC), data retransmission, or a combination of both to detect and deal with these run-time faults. The problem is that these test approaches have a cost in terms of, for instance, silicon area, codec delay, network congestion, and energy consumption. Thus, the challenge for the designer is to find a good trade-off between these costs and the potential benefit of the test approach in terms of reliability. This chapter presents the most relevant on-line NoC testing strategies that have been proposed and their results about the compromise of costs and reliability.
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References
Bertozzi D, Benini L, De Micheli G (2005) Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans Comput-Aided Des Integr Circuits Syst 24(6):818–831
Frantz AP, Cassel M, Kastensmidt FL, Cota E, Carro L (2007) Crosstalk- and SEU-aware networks on chips. IEEE Des Test Comput 24(4):340–350
Ganguly A, Pande PP, Belzer B, Grecu C (2008) Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding. J Electron Test 24(1–3):67–81
Lehtonen T, Liljeberg P, Plosila J (2007) Online reconfigurable self-timed links for fault tolerant NoC. VLSI Des Hindawi 2007:13
Lehtonen T, Wolpert D, Liljeberg P, Plosila J, Ampadu P (2010) Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans Very Large Scale Integr (VLSI) Syst 18(4):527–540
Murali S, Theocharides T, Vijaykrishnan N, Irwin MJ, Benini L, De Micheli G (2005) Analysis of error recovery schemes for networks on chips. IEEE Des Test Comput 22(5):434–442
Sridhara SR, Shanbhag NR (2005) Coding for system-on-chip networks: a unified framework. IEEE Trans Very Large Scale Integr (VLSI) Syst 13(6):655–667
Vellanki P, Banerjee N, Chatha KS (2005) Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integr VLSI J 38(3):353–382
Victor B, Keutzer K (2001) Bus encoding to prevent crosstalk delay. In: Proceedings of the international conference on computer-aided design (ICCAD), San Jose, California, pp 57–63
Yu Q, Ampadu P (2010) Transient and permanent error co-management method for reliable networks-on-chip. In: Proceedings of the international symposium on networks-on-chip (NOCS), Grenoble, France, pp 145–154
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Cota, É., de Morais Amory, A., Lubaszewski, M.S. (2012). Error Control Coding and Retransmission. In: Reliability, Availability and Serviceability of Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0791-1_8
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DOI: https://doi.org/10.1007/978-1-4614-0791-1_8
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