Abstract
As the number of IP modules in Systems-on-Chip (SoCs) increases, bus-based interconnection architectures may prevent these systems to meet the performance required by many applications. For systems with intensive parallel communication requirements buses may not provide the required bandwidth, latency, and power consumption. A solution for such a communication bottleneck is the use of an embedded switching network, called Network-on-Chip (NoC), to interconnect the IP modules in SoCs. NoCs design space is considerably larger when compared to a bus-based solution, as different routing and arbitration strategies can be implemented as well as different organizations of the communication infrastructure. In addition, NoCs have an inherent redundancy that helps tolerate faults and deal with communication bottlenecks. This enables the SoC designer to find suitable solutions for different system characteristics and constraints.
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Cota, É., de Morais Amory, A., Lubaszewski, M.S. (2012). NoC Basics. In: Reliability, Availability and Serviceability of Networks-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0791-1_2
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DOI: https://doi.org/10.1007/978-1-4614-0791-1_2
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