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Statistical Power Grid Analysis Considering Log-Normal Leakage Current Variations

  • Ruijing Shen
  • Sheldon X.-D. Tan
  • Hao Yu
Chapter

Abstract

As discussed in Part II, process-induced variability has huge impacts on chip leakage currents, owing to the exponential relationship between subthreshold leakage current I sub and threshold voltage V th as shown below[172],
$$\begin{array}{rcl}{ I}_{\mathrm{sub}} = {I}_{s0}{e}^{\frac{{V}_{gs}-{V}_{\mathrm{th}}} {n{V}_{T}} }\left (1 -{\mathrm{e}}^{\frac{-{V}_{ds}} {{V}_{T}} }\right ),& &\end{array}$$
(8.1)
where I s0 is a constant related to the device characteristics, V T is the thermal voltage, and n is a constant. It was shown in[78] that leakage variations for 90nm can be 20 ×. Based on the ITRS[71], the leakage power accounts for more than 60% at 45nm; there are many consequences for chip design, especially for design of the power grid.

Keywords

Leakage Current Power Grid Node Voltage Threshold Voltage Versus Sleep Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Ruijing Shen
    • 1
  • Sheldon X.-D. Tan
    • 1
  • Hao Yu
    • 2
  1. 1.Department of Electrical EngineeringUniversity of CaliforniaRiversideUSA
  2. 2.Department of Electrical and ElectronicNanyang Technological UniversitySingaporeSingapore

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