Abstract
How would you create a complex class for a bus transaction that also performs error injection and has random delays? The first approach is to put everything in a large, flat class. This approach is simple to build, easy to understand (all the code is right there in one class) but can be slow to develop and debug. Additionally, such a large class is a maintenance burden, as anyone who wants to make a new transaction behavior has to edit the same file. Just as you would never create a complex RTL design using just one Verilog module, you should break classes down into smaller, reusable blocks.
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© 2012 Springer Science+Business Media, LLC
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Spear, C., Tumbush, G. (2012). Advanced OOP and Testbench Guidelines. In: SystemVerilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0715-7_8
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DOI: https://doi.org/10.1007/978-1-4614-0715-7_8
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