Abstract
As you verify your design, you need to write a great deal of code, most of which is in tasks and functions. SystemVerilog introduces many incremental improvements to make this easier by making the language look more like C, especially around argument passing. If you have a background in software engineering, these additions should be very familiar.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsAuthor information
Authors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Spear, C., Tumbush, G. (2012). Procedural Statements and Routines. In: SystemVerilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0715-7_3
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0715-7_3
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4614-0714-0
Online ISBN: 978-1-4614-0715-7
eBook Packages: EngineeringEngineering (R0)