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Abstract

An important goal in VLSI designs is represented by the possibility of a multiple utilization of the same cell, the increased modularity that can be achieved being reflected in an important reduction of power consumption and of design costs per circuit function. Many fundamental linear or nonlinear analog blocks can be realized starting from the same core, the optimization technique implemented for the nucleus being efficient for all the derived circuits. The presented multifunctional structures are based on four different elementary mathematical principles, each of them being illustrated by concrete implementations in CMOS technology of their functional relations.

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References

  1. Popa C (2010) Improved linearity CMOS differential amplifiers with applications in VLSI designs. International symposium on electronics and telecommunications, pp 29–32, Timisoara, Romania

    Google Scholar 

  2. Popa C (2009) High accuracy CMOS multifunctional structure for analog signal processing. International semiconductor conference, pp 427–430, Sinaia, Romania

    Google Scholar 

  3. Popa C (2010) CMOS multifunctional computational structure with improved performances. International semiconductors conference, pp 471–474, Sinaia, Romania

    Google Scholar 

  4. Popa C (2006) CMOS quadratic circuits with applications in VLSI designs. International conference on signals and electronic systems, pp 117–120, Lodz, Poland

    Google Scholar 

  5. Popa C (2004) A digital-selected current-mode function generator for analog signal processing applications. International semiconductor conference, pp 495–498, Sinaia, Romania

    Google Scholar 

  6. Popa C (2005) Improved accuracy pseudo-exponential function generator with applications in analog signal processing. International conference on computer as a tool, 1594–1597, Belgrade, Serbia and Montenegro

    Google Scholar 

  7. Popa C (2008) Improved accuracy pseudo-exponential function generator with applications in analog signal processing. IEEE Trans Very Large Scale Integr Syst 16:318–321

    Article  Google Scholar 

  8. De La Cruz Blas CA, Feely O (2008) Limit cycle behavior in a class-AB second-order square root domain filter. IEEE international conference on electronics, circuits and systems, pp 117–120, St. Julians, Malta

    Google Scholar 

  9. Zarabadi SR, Ismail M, Chung-Chih H (1998) High performance analog VLSI computational circuits. IEEE J Solid-State Circuits 33:644–649

    Article  Google Scholar 

  10. Sakurai S, Ismail M (1992) A CMOS square-law programmable floating resistor independent of the threshold voltage. IEEE Trans Circuits Syst II: Analog Digit Signal Process 39:565–574

    Article  Google Scholar 

  11. Popa C, Manolescu AM (2007) CMOS differential structure with improved linearity and increased frequency response. International semiconductor conference, pp 517–520, Sinaia, Romania

    Google Scholar 

  12. Popa C (2010) Tunable CMOS resistor circuit with improved linearity based on the arithmetical mean computation. IEEE Mediterranean electrotechnical conference, pp 1379–1382, Valletta, Malta

    Google Scholar 

  13. Manolescu AM, Popa C (2009) Low-voltage low-power improved linearity CMOS active resistor circuits. Springer J Analog Integr Circuits Signal Process 62:373–387

    Article  Google Scholar 

  14. Lee BW, Sheu BJ (1990) A high slew-rate CMOS amplifier for analog signal processing. IEEE J Solid-State Circuits 25:885–889

    Article  Google Scholar 

  15. Kumar JV, Rao KR (2002) A low-voltage low power square-root domain filter. Asia-Pacific conference on circuits and systems, pp 375–378, Bali, Indonesia

    Google Scholar 

  16. Klumperink E, van der Zwan E, Seevinck E (1989) CMOS variable transconductance circuit with constant bandwidth. Electron Lett 25:675–676

    Article  Google Scholar 

  17. Zele RH, Allstot DJ, Fiez TS (1991) Fully-differential CMOS current-mode circuits and applications. IEEE international symposium on circuits and systems, pp 1817–1820, Raffles City, Singapore

    Google Scholar 

  18. El Mourabit A, Sbaa MH, Alaoui-Ismaili Z, Lahjomri F (2007) A CMOS transconductor with high linear range. IEEE international conference on electronics, circuits and systems, pp 1131–1134, Marrakech, Morocco

    Google Scholar 

  19. Popa C (2008) Programmable CMOS active resistor using computational circuits. International semiconductor conference, pp 389–392, Sinaia, Romania

    Google Scholar 

  20. Farshidi E (2009) A low-voltage class-AB linear transconductance based on floating-gate MOS technology. European conference on circuit theory and design, pp 437–440, Antalya, Turkey

    Google Scholar 

  21. Abbasi M, Kjellberg T et al (2010) A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip. IEEE radio frequency integrated circuits symposium, pp 533–536, Anaheim, USA

    Google Scholar 

  22. Yonghui J, Ming L et al (2010) A low power single ended input differential output low noise amplifier for L1/L2 band. IEEE international symposium on circuits and systems, pp 213–216, Paris, France

    Google Scholar 

  23. Ong GT, Chan PK (2010) A micropower gate-bulk driven differential difference amplifier with folded telescopic cascode topology for sensor applications. IEEE international midwest symposium on circuits and systems, pp 193–196, Seattle, USA

    Google Scholar 

  24. Vaithianathan V, Raja J, Kavya R, Anuradha N (2010) A 3.1 to 4.85 GHz differential CMOS low noise amplifier for lower band of UWB applications. International conference on wireless communication and sensor computing, pp 1–4, Chennai, India

    Google Scholar 

  25. Figueiredo M, Santin E, Goes J, Santos-Tavares R, Evans G (2010) Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency. IEEE international symposium on circuits and systems, pp 2828–2831, Paris, France

    Google Scholar 

  26. Enche Ab, Rahim SAE, Ismail MA et al (2010) A wide gain-bandwidth CMOS fully-differential folded cascode amplifier. International conference on electronic devices, systems and applications, pp 165–168, Kuala Lumpur, Malaysia

    Google Scholar 

  27. Chanapromma C, Daoden K (2010) A CMOS fully differential operational transconductance amplifier operating in sub-threshold region and its application. International conference on signal processing systems, pp V2-73–V2-7728, Yantai, China

    Google Scholar 

  28. Rajput KK, Saini AK, Bose SC (2010) DC offset modeling and noise minimization for differential amplifier in subthreshold operation. IEEE computer society annual symposium on VLSI, pp 247–252, Greece

    Google Scholar 

  29. Bajaj N, Vermeire B, Bakkaloglu B (2010) A 10 MHz to 100 MHz bandwidth scalable, fully differential current feedback amplifier. IEEE international symposium on circuits and systems, pp 217–220, Paris, France

    Google Scholar 

  30. Harb A (2010) A rail-to-rail full clock fully differential rectifier and sample-and-hold amplifier. IEEE international symposium on circuits and systems, pp 1571–1574, Paris, France

    Google Scholar 

  31. Lili C, Zhiqun L et al (2010) A 10-Gb/s CMOS differential transimpedance amplifier for parallel optical receiver. International symposium on signals systems and electronics, pp 1–4, Nanjing, China

    Google Scholar 

  32. Popa C (2009) Computational circuits using bulk-driven MOS devices. IEEE international conference on computer as a tool, pp 246–251, St. Petersburg, Russia

    Google Scholar 

  33. Popa C (2009) Multiplier circuit with improved linearity using FGMOS transistors. International symposium ELMAR, pp 159–162, Zadar, Croatia

    Google Scholar 

  34. Popa C (2001) Low-power rail-to-rail CMOS linear transconductor. International semiconductor conference, pp 557–560, Sinaia, Romania

    Google Scholar 

  35. Wallinga H, Bult K (1989) Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model. IEEE J Solid-State Circuits 24:672–680

    Article  Google Scholar 

  36. Sawigun C, Serdijn WA (2009) Ultra-low-power, class-AB, CMOS four-quadrant current multiplier. Electron Lett 45:483–484

    Article  Google Scholar 

  37. Akshatha BC, Akshintala VK (2009) Low voltage, low power, high linearity, high speed CMOS voltage mode analog multiplier. International conference on emerging trends in engineering and technology, pp 149–154, Nagpur, India

    Google Scholar 

  38. Hidayat R, Dejhan K, Moungnoul P, Miyanaga Y (2008) OTA-based high frequency CMOS multiplier and squaring circuit. International symposium on intelligent signal processing and communications systems, pp 1–4, Bangkok, Thailand

    Google Scholar 

  39. Naderi A et al (2009) Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed. IEEE international conference on computer as a tool, pp 282–287, St. Petersburg, USA

    Google Scholar 

  40. Khateb F, Biolek D, Khatib N, Vavra J (2010) Utilizing the bulk-driven technique in analog circuit design. IEEE international symposium on design and diagnostics of electronic circuits and systems, pp 16–19, Vienna, Austria

    Google Scholar 

  41. Machowski W, Kuta S, Jasielski J, Kolodziejski W (2010) Quarter-square analog four-quadrant multiplier based on CMOS invertes and using low voltage high speed control circuits. International conference on mixed design of integrated circuits and systems, pp 333–336, Wroklaw, Poland

    Google Scholar 

  42. Ehsanpour M, Moallem P, Vafaei A (2010) Design of a novel reversible multiplier circuit using modified full adder. International conference on computer design and applications, pp V3-230–V3–234, Hebei, China

    Google Scholar 

  43. Parveen T, Ahmed MT (2009) OFC based versatile circuit for realization of impedance converter, grounded inductance, FDNR and component multipliers. International multimedia, signal processing and communication technologies, pp 81–84, Aligarh, India

    Google Scholar 

  44. Feldengut T, Kokozinski R, Kolnsberg S (2009) A UHF voltage multiplier circuit using a threshold-voltage cancellation technique. Research in microelectronics and electronics, pp 288–291, Cork, Ireland

    Google Scholar 

  45. Popa C (2009) Logarithmic compensated voltage reference. Spanish conference on electron devices, pp 215–218, Santiago de Compostela, Spain

    Google Scholar 

  46. Popa C (2007) Improved accuracy function generator circuit for analog signal processing. International conference on computer as a tool, pp 231–236, Warsaw, Poland

    Google Scholar 

  47. Cheng-Chieh C, Shen-Iuan L (2000) Current-mode full-wave rectifier and vector summation circuit. Electron Lett 36:1599–1600

    Article  Google Scholar 

  48. Hidayat R, Dejhan K, Moungnoul P, Miyanaga Y (2008) OTA-based high frequency CMOS multiplier and squaring circuit. International symposium on intelligent signal processing and communications systems, pp 1–4, Bangkok, Thailand

    Google Scholar 

  49. Kumbun J, Lawanwisut S, Siripruchyanun M (2009) A temperature-insensitive simple current-mode squarer employing only multiple-output CCTAs. IEEE region 10 conference TENCON, pp 1–4, Singapore

    Google Scholar 

  50. Naderi A, Mojarrad H, Ghasemzadeh H, Khoei A, Hadidi K (2009) Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed. IEEE international conference on computer as a tool, pp 282–287, St Petersburg, Russia

    Google Scholar 

  51. Machowski W, Kuta S, Jasielski J, Kolodziejski W (2010) Quarter-square analog four-quadrant multiplier based on CMOS invertes and using low voltage high speed control circuits. International conference on mixed design of integrated circuits and systems, pp 333–336, Wroclaw, Poland

    Google Scholar 

  52. Raikos G, Vlassis S (2009) Low-voltage CMOS voltage squarer. IEEE international on electronics, circuits, and systems, pp 159–162, Medina, Tunisia

    Google Scholar 

  53. Muralidharan R, Chip-Hong C (2009) Fixed and variable multi-modulus squarer architectures for triple moduli base of RNS. IEEE international conference on circuits and systems, pp 441–444, Taipei, Taiwan

    Google Scholar 

  54. Garofalo V et al (2010) A novel truncated squarer with linear compensation function. IEEE international symposium on circuits and systems, pp 4157–4160, Paris, France

    Google Scholar 

  55. Kircay A, Keserlioglu MS (2009) Novel current-mode second-order square-root-domain highpass and allpass filter. International conference on electrical and electronics engineering, pp II-242–II-246, Bursa, Turkey

    Google Scholar 

  56. Kircay A, Keserlioglu MS, Cam U (2009) A new current-mode square-root-domain notch filter. European conference on circuit theory and design, pp 229–232, Antalya, Turkey

    Google Scholar 

  57. Popa C (2007) Improved linearity active resistors using MOS and floating-gate MOS transistors. The international conference on computer as a tool, pp 224–230, Warsaw, Poland

    Google Scholar 

  58. Popa C (2007) Low-voltage low-power curvature-corrected voltage reference circuit using DTMOSTs. Lecture notes in computer science, Springer, pp 117–124

    Google Scholar 

  59. Dermentzoglou LE, Arapoyanni A, Tsiatouhas Y (2010) A built-in-test circuit for RF differential low noise amplifiers. IEEE Trans Circuits Syst I: Regul Pap 57:1549–1558

    Article  MathSciNet  Google Scholar 

  60. De La Cruz-Blas CA, Lopez-Martin A, Carlosena A (2003) 1.5-V MOS translinear loops with improved dynamic range and their applications to current-mode signal processing. IEEE Trans Circuits Syst II: Analog Digit Signal Process 50:918–927

    Article  Google Scholar 

  61. Desheng M, Wilamowski BM, Dai FF (2009) A tunable CMOS resistor with wide tuning range for low pass filter application. IEEE topical meeting on silicon monolithic integrated circuits in RF systems, pp 1–4, San Diego, USA

    Google Scholar 

  62. Torralba A et al (2009) Tunable linear MOS resistors using quasi-floating-gate techniques. IEEE Trans Circuits Syst II: Exp Briefs 56:41–45

    Article  MathSciNet  Google Scholar 

  63. Tadić N, Zogović M (2010) A low-voltage CMOS voltage-controlled resistor with wide resistance dynamic range. International conference on microelectronics proceedings, pp 341–344, Nis, Serbia

    Google Scholar 

  64. Mandai S, Nakura T, Ikeda M, Asada K (2010) Cascaded time difference amplifier using differential logic delay cell. Asia and South Pacific design automation conference, pp 355–356, Taipei, Taiwan

    Google Scholar 

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Correspondence to Cosmin Radu Popa .

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Popa, C.R. (2012). Multifunctional Structures. In: Synthesis of Computational Structures for Analog Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0403-3_8

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  • DOI: https://doi.org/10.1007/978-1-4614-0403-3_8

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