Abstract
The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.
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Notes
- 1.
For simplicity, any HDL languages that this book refers to takes Verilog as an example.
References
Mohit Arora, Prashant Bhargava, Amit Srivastava, Optimization and Design Tips for FPGA/ASIC(How to make the best designs), DCM Technologies, SNUG India, 2002
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© 2012 Springer Science+Business Media, LLC
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Arora, M. (2012). Clocks and Resets. In: The Art of Hardware Architecture. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0397-5_2
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DOI: https://doi.org/10.1007/978-1-4614-0397-5_2
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