Abstract
As was mentioned in the previous chapter, device performance in mm-Wave frequencies is deeply under the influence of layout parasitics. Apart from the urge for layout dependent models, as was pointed out before, this has another important consequence: Unlike low frequency circuit design in which the device design is absolutely in the realm of process engineers, here the circuit designer could- and should- alter the device performance by changing the device layout [1, 3]. This enables the designer to layout the device based on the performance metric which is more important in any specific application. It might be astounding in the first look how much the device layout could vary certain device parameters. f max , for instance, which is an indicator of the speed of the transistor, have been reported for a similar process, CMOS 90 nm, from 80 GHz to up to 300 GHz mainly due to differences in layout [2, 8].
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Notes
- 1.
A general condition for N-port unilateralization is presented in Chap. 5.
- 2.
Noise analysis and optimization is discussed in Chap. 4.
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Gharavi, S., Heydari, B. (2011). mm-Wave Device Optimization. In: Ultra High-Speed CMOS Circuits. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0305-0_3
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DOI: https://doi.org/10.1007/978-1-4614-0305-0_3
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