Integrated Circuit Implementation

  • Bupesh PanditaEmail author
Part of the Analog Circuits and Signal Processing book series (ACSP)


The previous chapter discussed the architecture and system level considerations in the design of the proposed fourth-order complex ΔΣ modulator. The required specifications for each building block were also discussed in that chapter. This chapter discusses the implementation of each of these blocks in a 0.18 μm CMOS technology. Due to a high sampling clock frequency and the mixed-signal nature of the ADC, special care has to be taken to minimize the cross-talk of digital noise into the sensitive analog nodes. In Chap. 4, the impact of mismatch on the SNDR and IMR of the ADC was discussed. In the layout of the ADC, special attention must be paid to minimizing the mismatch between the real and the quadrature channels. The chapter discusses the layout considerations that were taken into account and the techniques that were followed during the layout of the proposed ΔΣ modulator.


Clock Generator Clock Phase Image Rejection Sampling Capacitor Polyphase Filter 
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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.AMDMarkhamCanada

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