Integrated process feasibility of hard-mask for tight pitch interconnects fabrication

Abstract

As scaling continues beyond nano-technology, integrated circuit reliability is gaining increasing concerns in IC (Integrated Circuit) fabrication technology with decreasing transistor gate size, and the impact of trace interconnect failure mechanisms on device performance and reliability will demand much more from integration schemes, interconnect materials, and processes. An optimal low-k dielectric material and their related deposition, pattern lithography, etching and cleaning are required to form dual-damascene interconnect patterns fabrication processes. As technology nodes advance to nanotechnology, metal hard-mask such as TiN is used to gain better etching selectivity and profile controlling to the low-k materials during the pattern etching process. A hard-mask scheme approach of interconnects patterning of wafer fabrication is the ability to transfer patterns into under layers with tightest optimal dimension control. Employing a hard-mask scheme in the fabrication process, successfully achieved lithography patterning, dry etch selectivity in high aspect ratio interconnects comparison with a non hard-mask process were discussed. An optimal planarization treatment of photo-resist, good etch selectivity, a feasible manufacturing integrated process of hard mask dual damascene scheme, optimal profile controlling the critical interconnects and good electrical device performances were studied for tight pitch damascene interconnect architecture.