Abstract
In the previous three Chaps.4, 5, and 6, design and analysis of delay-insensitive and high-performance on-chip interconnects have been presented. These interconnects are suitable for any kind of point-to-point on-chip communication, such as in a SoC to connect nearby or far away system blocks and in a NoC between two routers. The purpose of this chapter is to make a generalized summary of the presented interconnects as well as comparisons between them. In order to do so, all interconnects are redesigned and simulated in 65nm CMOS technology from STMicroelectronics with 1V supply voltage.
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© 2012 Springer Science+Business Media, LLC
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Nigussie, E.E. (2012). Comparison of the Designed Interconnects. In: Variation Tolerant On-Chip Interconnects. Analog Circuits and Signal Processing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0131-5_7
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DOI: https://doi.org/10.1007/978-1-4614-0131-5_7
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-0130-8
Online ISBN: 978-1-4614-0131-5
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