Enhancing Completion Detection Performance

Abstract

In the previous chapter, designs of high-performance and delay-insensitive current sensing interconnects have been presented. In delay-insensitive transmission, validity of the data is encoded within the data itself at the transmitter, and the data validity test, i.e., completion detection, as well as data decoding is performed at the receiver. The delay incurred due to completion detection increases with bit width of the transmission channel and affects the performance of the communication significantly. In order to overcome this overhead, a high speed completion detection technique along with its CMOS implementation is designed and presented in this chapter. Unlike the conventional detection circuits, the delay of the presented completion detection circuit is not affected by the bit width of the channel. This optimizes the performance of delay-insensitive current sensing links further since it was already demonstrated in Chap.4 that the current sensing interconnects achieve higher performance and better power efficiency than the interconnects using voltage-mode signaling with repeaters or pipelines.