On-Chip Wire Modeling

Abstract

A chip is non-functional without wires that connect devices each other. Wires carry signals from one place to another. On-chip wires constitute the lowest level in a hierarchy that spans chip to package-level connections. On-chip wire is not an ideal conductor with zero resistance, capacitance and inductance, but rather it is an unwanted parasitic circuit element. With the increase in circuit performance, complexity, density and levels of integration in nanometer technologies, it is essential to include all parasitic effects during the optimization process. However, this is not a feasible approach due to the large amount of design variables in the optimization process and the overall complexity of the chip. Furthermore, this approach has the disadvantage of not seeing the exact problem, because at a given circuit node, only few dominant parameters affect the overall performance. Thus, designers need to have a clear insight into the parasitic wiring effects, their relative importance and their reduced-order models. Wire parasitics estimation is required to compare different interconnect schemes because interconnect figures of merits (performance, power consumption and noise coupling) [98, 99] are functions of wire parasitics. In this book a wire refers to just the metal that interconnects different blocks and the interconnect refers to a wire with its driver and data encoder, load (receiver input impedance) and receiver along with data decoder and completion detector. This chapter discusses briefly methods and basis for estimating wire parasitics and the electrical level modeling of wires.