A 130-nm CMOS Reconfigurable 2-1-1 Cascade SC ΣΔM for GSM/BT/UMTS
BEYOND-3G WIRELESS TELECOM SYSTEMS WILL REQUIRE low-power multi-standard chipsets that are capable to operate over a number of different co-existing communication protocols, signal conditions, battery status, etc. [Bran05]. An efficient implementation of these chipsets demands for reconfigurable transceiver blocks that can adjust their circuit parameters to the diverse specifications with adaptive power consumption and at the lowest cost. One of the most challenging building blocks in multi-standard receivers is the ADC, because of the assorted signal bandwidths and dynamic ranges that can be required to properly handle the A/D conversion for several operation modes [Gula01]. Compared to other data conversion techniques, SD modulators are very suited for the implementation of multi-standard, multi-mode ADCs in highly integrated transceivers using low-cost digitally-oriented nanometer CMOS technologies. On the one hand, the key principles of SD modulators (oversampling and noise shaping) make them robust with respect to circuit errors. On the other, since both principles determine the dynamic range of the SD modulator, their variations can easily contribute to adapt the converter performance to different specifications with large hardware reuse [Burg01][Mill03][Veld03][Chri07][Crom09].