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Scalable Shared Memory MIMD Computers

  • Burton J. Smith
Conference paper

Abstract

Why are shared memory MIMD computers with many processors difficult to implement? The answer depends in part on the definition of the term “shared memory”, but there is probably broad agreement that any sort of shared memory system with hundreds of processors is a challenge. The main problem is the latency associated with memory access and its consequences for processor performance. There are two possible solutions to this problem, namely latency avoidance and latency tolerance. Latency avoidance is accomplished by arranging a processor’s memory accesses so that most of them are to locations that are both spatially and temporally nearby. Latency tolerance is brought about through the use of additional parallelism. Both ideas have been used in shared memory systems, with varying success.

Keywords

Cache Line Virtual Processor Shared Memory System Memory Interference Physical Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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Copyright information

© Springer-Verlag New York Inc. 1989

Authors and Affiliations

  • Burton J. Smith
    • 1
  1. 1.Tera Computer CompanyUSA

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