Scalable Shared Memory MIMD Computers
Why are shared memory MIMD computers with many processors difficult to implement? The answer depends in part on the definition of the term “shared memory”, but there is probably broad agreement that any sort of shared memory system with hundreds of processors is a challenge. The main problem is the latency associated with memory access and its consequences for processor performance. There are two possible solutions to this problem, namely latency avoidance and latency tolerance. Latency avoidance is accomplished by arranging a processor’s memory accesses so that most of them are to locations that are both spatially and temporally nearby. Latency tolerance is brought about through the use of additional parallelism. Both ideas have been used in shared memory systems, with varying success.
KeywordsCache Line Virtual Processor Shared Memory System Memory Interference Physical Processor
- [ [GKLS83]D. Gajski, D. Kuck, D. Lawrie, and A. Sameh, “CEDAR—A Large Scale Multiprocessor”, Proc. 1983 International Conference on Parallel Processing, pp. 524–529.Google Scholar
- [PBGH85]G. Pfister, W. Brantley, D. George, S. Harvey, W. Kleinfelder, K. McAuliffe, E. Melton, V. Norton, and J. Weiss, “The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture”, Proc. 1985 International Conference on Parallel Processing, pp. 764–771.Google Scholar
- [LeYL87]R. L. Lee, P-C. Yew, and D. H. Lawrie, “Multiprocessor Cache Design Considerations”, Proc. 14th Annual International Symposium on Computer Architecture pp. 253–262 (1987).Google Scholar
- [ArCu86]Arvind and D. E. Culler, “Dataflow Architectures”, Annual Review of Computer Science 1986 1, pp. 225–253.Google Scholar
- [Smit78]B. J. Smith, “A Pipelined, Shared Resource MIMD Computer”, Proc. 1978 International Conference on Parallel Processing, pp. 6–8.Google Scholar