Abstract
In this chapter we discuss our computational experience with an APL implementation of ESPRESSO-II. We report data on 56 PLA’s given to us by various sources. Some have already been minimized by various PLA minimization programs while others consist entirely of minterms. The 56 PLA’s are a mixture of control and data flow logic. Some have don’t-care sets and there is a range in size from 4 inputs to 94 inputs, from 1 output to 109 outputs, and from an initial cover size of 10 terms to 654 terms. The computing time required by ESPRESSO-IIAPL to minimize these PLA’s ranged from less than a second to 721 seconds on an IBM/3081K machine. Most of the PLA’s represent real applications although a few are arithmetic functions which we devised for their interesting structures, or because they were known to be difficult problems.
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© 1984 Kluwer Academic Publishers
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Brayton, R.K., Hachtel, G.D., McMullen, C.T., Sangiovanni-Vincentelli, A.L. (1984). Experimental Results. In: Logic Minimization Algorithms for VLSI Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 2. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2821-6_6
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DOI: https://doi.org/10.1007/978-1-4613-2821-6_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-9784-0
Online ISBN: 978-1-4613-2821-6
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