Abstract
As discussed in Chapter 1, many multiple-valued input logic functions can be implemented very efficiently in PLA’s with two-bit input decoders. Hence multiple-valued logic minimization is of great practical importance [FLE 75]. A two-bit decoder pairs two Boolean variables, say x1 and x2, and generates four decodes
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© 1984 Kluwer Academic Publishers
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Brayton, R.K., Hachtel, G.D., McMullen, C.T., Sangiovanni-Vincentelli, A.L. (1984). Multiple-Valued Logic Minimization. In: Logic Minimization Algorithms for VLSI Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 2. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2821-6_5
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DOI: https://doi.org/10.1007/978-1-4613-2821-6_5
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-9784-0
Online ISBN: 978-1-4613-2821-6
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