Abstract
Silicon integrated circuit (IC) technology has evolved to fabricate multi-million transistors on a single chip. Trial-and-error methodology to optimize such a complex process is no longer desirable because of the enormous cost and turn-around time. From this point of view, computer simulation is a cost-effective alternative, not only supplying a right answer for increasingly tight processing windows, but also serving as a tool to develop future technologies. When coupled with a device analysis program, a process simulator has proven to be a powerful design tool because the process sensitivity to device parameters can be easily extracted by simple changes made to processing conditions in computer inputs. [2.1].
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Reference
D. A. Antoniadis, S. E. Hansen, R. W. Dutton, and A. G. Gonzales, “SUPREM I — A Program for IC Process Modeling and Simulation”, SEL 77-006, Stanford Electronics La bora ties, Stanford University, Calif., May 1977.
D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREM II — A Program for IC Process Modeling and Simulation,” TR 5019. 2, Stanford Electronics Laboratories, Stanford University, Calif., June 1978.
C. P. Ho and S. E. Hansen, “SUPREM III — A Program for IC Process Modeling and Simulation,” TR SEL 83-001, Stanford Electronics Laboratories, Stanford University, Calif., July 1983.
D. Chin, M. R. Kump, and R. W. Dutton, “SUPRA: Stanford University PRocess Analysis Program,” Stanford University Laboratories, Stanford University, Stanford, Calif., July 1981.
D. Chin, M. R. Kump, H. G. Lee, and R. W. Dutton, Process Design Using Two-Dimensional Process and Device Simulators, IEEE Trans, on Electron Devices ED-29, Feb. 1982, pp. 336–340.
D. Chin and R. W. Dutton, “SOAP: Stanford Oxidation Analysis Program,” Stanford University Laboratories, TR SEL 83-002, Stanford University, Stanford, Calif. Aug. 1983.
B. R. Penumalli, “A Comprehensive Two-Dimensional VLSI Process Simulation Program” — BICEPS, IEEE Trans, on Electron Devices ED-36, Sept 1983, pp. 986–992.
G. E. Smith, III, and A. J. Steckl, “RECIPE — A Two-Dimensional VLSI Modeling Program,”IEEE Trans, on Electron Devices ED-29, Feb. 1982, pp. 216–221.
K. A. Salsburg, and H. H. Hensen, “FEDSS — Finite-Element Diffusion — Simulation System,”IEEE Trans, on Electron Devices ED-30, Sept 1983, pp. 1004–1011.
J. Lindhard, M. Scharff, and M. Schiott, Mat. Fys. Medd. Dan. Vid. Sclsk. (33), 1963.
B. E. Deal and A. S. Grove, “General Relationship for the thermal Oxidation of Silicon,”J. Appl. Phys, 36 (12), Dec 1965, pp. 3770–3778.
C. P. Ho, J. D. Plummer, B. E. Deal, and J. D. Meindl, “Thermal Oxidation of Heavily Phosphorus Doped Silicon,”J. Electrochem. Soc., 125, Apr 1978, pp. 665–671.
H. Z. Massoud, “Thermal Oxidation of Silicon in Dry Oxygen — Growth Kinetics and Charge Characterization in the Thin Regime,” Stanford Electronics Laboratories, TR G502-1, Stanford University, Stanford, Calif., June 1983.
R. O. Schwenker, E. S. Pan, and R. F. Lever, “Arsenic Clustering in Silicon,”J. Appl. Phys., 42, 1971, pp. 3195–3200.
R. B. Fair and J. C. C. Tsai, “A Quantitative Model for the Diffusion of Phosphorus in Silicon and the Emitter Dip Effect,”J. Electrochem. Soc., 124, July 1977, pp. 1107–1121.
H. Runge, “Distribution of Implanted Ions under Arbitrarily Shaped Mask Regions,”Phys. Stat. Sol. (a), vol. 39, 1977, pp. 595–599.
J. Huang and L. Welliver, “on the Redistribution of Boron in the Diffused Layer during Thermal Oxidation,”J. Electrochem. Soc., vol. 117, 1970, pp. 1577–1580.
H. G. Lee, R. W. Dutton, and D. A. Antoniadis, “On Redistribution of Boron during Thermal Oxidation of Silicon,”J. Electronchem. Soc., vol. 126, 1979, pp. 2001–2007.
M. R. Kump and R. W. Dutton, “An Overview of Process Models and Two-Dimensional Analysis Tools,” Stanford Electronics Laboratories, TR G-201-13, Stanford University, Stanford, Calif., July 1982.
J. A. Greenfield and R. W. Dutton, “Nonplanar VLSI Device Analysis the Solution of Poisson’s Equation,”IEEE Trans. on Electron Devices, ED-27, Aug 1980, pp. 1520–1532.
R. B. Marcus and T. T. Sheng, “The Thermal Oxidation of Shaped Silicon Surfaces,”J. of Electrochem. Soc., 129, June 1982, pp. 1278–1289.
L. O. Wilson, “Numerical Simulation of Gate Oxide Thinning in MOS Devices,”J. Electrochem,. Soc., 129, Apr 1982, pp. 831–837.
D. Chin, i. Oh, S. M. Hu and J. L. Moll, Two-Dimensional Modeling of Local Oxidation, presented at Device Research Conference, olorado, June 1982.
E. P. EerNisse, “Viscous Flow of SiO2,”, Appl. Phys. Lett., 30, 1977, pp. 290–293.
E. P. EerNisse, “Stress in Thermal SiO2 during Growth,”Appl Phys. Lett., 35, 1979, pp. 8–10.
D. Chin, S. Y. Oh, R. W. Dutton, and J. L. Moll, “Two-Dimensional Oxidation Modeling,”IEEE Trans, on Electron Devices, ED-30, July 1983, pp. 744–749.
D. Chin, S. Y. Oh, R. W. Dutton, and J. L. Moll, “Two-Dimensional Local Oxidation,”IEEE Trans. on Electron Devices, ED-30, Sept 1983, pp. 993–999.
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Cham, K.M., Oh, SY., Chin, D., Moll, J.L. (1986). Process Simulation. In: Computer-Aided Design and VLSI Device Development. The Springer International Series in Engineering and Computer Science, vol 7. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2553-6_3
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DOI: https://doi.org/10.1007/978-1-4613-2553-6_3
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