Parasitics Extraction for VLSI Process Development

Abstract

Circuit performance in general depends on two major factors. These are transistor performance, and parasitic capacitances and resistances. The scaling down of geometrical dimensions introduces two-dimensional and even three-dimensional effects both in transistor behavior and in the parasitics. The scaling of interconnections is usually emphasized primarily in the width and spacing of the lines. For example, the line/space design rule (in micrometer units) for the first level aluminum in CMOS SRAMs has been scaled from 2.5/3.5 in 16Kb chips to 2/2 in 64Kb chips to 1.2/1.6 in 256Kb chips [13.1],[13.2]. The line thickness is often scaled down by a smaller factor in order to reduce the parasitic resistance, and to increase the reliability against electromigration [13.3],[13.4]. The increase in aspect ratio of the interconnect line thickness to line width and space increases the fringing and interline capacitance component in the total parasitic capacitance of a circuit. This means that the parasitic capacitance is not scaled down proportionally as the horizontal dimensions are scaled down.