Fabrication Processes

  • Marco Annaratone
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 16)


CMOS processes are generally more complex and expensive than nMOS processes because extra steps and extra masks are required in the fabrication process. Although many different processes are available, all the CMOS processes fall into either one of the two following classes:
  • Bulk processes: the substrate is doped silicon. Examples of bulk processes are p-well, n-well, and twin-tub. Newer bulk processes [18,32] can also have bipolar transistors on the same wafer, which has positive effects on driving capability — which is not as high in MOS as in bipolar technology — and when digital/analog applications — such as sense amplifiers in memory design [17] — are considered.

  • Silicon-on-insulator (SOI) processes: the substrate is an insulator, such as sapphire (“silicon-on-sapphire,” SOS) or silicon dioxide (SiO2).


Fabrication Process Parasitic Capacitance CMOS Process Bipolar Transistor Solid State Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Adams, J.R. and R.J. Sokel. Neutron Irradiation for Prevention of Latch-up in MOS Integrated Circuits. IEEE Trans. on Nuclear Science NS-26(6): 5069–5073, 1979.CrossRefGoogle Scholar
  2. [2]
    Anagnostopoulos, C.N. et al.. Latch-Up and image Crosstalk Suppression by Internal Gettering. IEEE Journal of Solid State Circuits SC-19(1):91–97, February, 1984.CrossRefGoogle Scholar
  3. [3]
    Appels, J.A. and M.M. Paffen. Local Oxidation of Silicon. Philips Res. Reports 26: 157–165, 1971.Google Scholar
  4. [4]
    Brandt, B.B.M., W. Steinmaier and A.J. Strachan. LOCMOS, a New Technology for Complementary MOS Circuits. Philips Technical Review 34 (1): 19–23, 1974.Google Scholar
  5. [5]
    Chatterjee, P. Device Design Issues for Deep Submicron VLSI. In Proc. of the 1985 International Symposium on VLSI Technology, Systems and Applications — Taiwan, pages 221–226. May, 1985.Google Scholar
  6. [6]
    Chen, M.-L., B.C. Leung and B. Lalevic. A High-performance CMOS/SOS Device with a Gradually Doped Source-Drain Extension Structure. IEEE Electrons Device Letters EDL-4(10):372–374, October, 1983.Google Scholar
  7. [7]
    Elmasry, M.I. Digital Bipolar Integrated Circuits. John Wiley & Sons, 1983.Google Scholar
  8. [8]
    Estreich, D.B., A. Ochoa and R.W. Dutton. An Analysis of Latch-up Prevention in CMOS IC’s Using an Epitaxial Buried Layer Process. In IEDM Tech. Dig.. December, 1978.Google Scholar
  9. [9]
    Genda, J.H. An Improved Model for Latch-up in CMOS Structures. In Proc. of the 1983 International Symposium on VLSI, Technology, Systems and Applications — Taiwan, pages 99–103. April, 1983.Google Scholar
  10. [10]
    Hashimoto, K. et al.. Counter-doped Well Structure for Scaled CMOS. In IEDM Tech. Dig.. December, 1982.Google Scholar
  11. [11]
    Isobe, M. et al.. An 18 ns CMOS/SOS 4K Static RAM. IEEE Journal of Solid State Circuits SC-16(5):460–465, October, 1981.CrossRefGoogle Scholar
  12. [12]
    Lam, H.W. Silicon on Insulating Substrates — Recent Advances. In IEDM Tech. Dig., pages 348–351. 1983.Google Scholar
  13. [13]
    Lim, H.K. and J.G. Fossum. A Charge-Based Large-Signal Model for Thin-Film SOI MOSFET’s. IEEE Journal of Solid State Circuits SC-20(1):366–377, February, 1985.Google Scholar
  14. [14]
    Manoliu et al. High-Density and Reduced Latchup Susceptibility CMOS Technology for VLSI. IEEE Electron Device Letters EDL-4(7):240–245, July, 1983.Google Scholar
  15. [15]
    Mayer, D.C. et al. A Short-Channel CMOS/SOS Technology in Recrystallized 0.3-μm-Thick Silicon-on-Sapphire Films. IEEE Electron Device Letters EDL-5(5):156–158, May, 1984.CrossRefGoogle Scholar
  16. [16]
    Mead, C. and L. Conway. Introduction To VLSI Systems. Addison-Wesley Publishing Co., Reading, Mass., 1980.Google Scholar
  17. [17]
    Miyamoto, J.I. et al.. A High-Speed 64K CMOS RAM with Bipolar Sense Amplifiers. IEEE Journal of Solid-State Circuits SC-19(5):557–563, October, 1984.MathSciNetCrossRefGoogle Scholar
  18. [18]
    Momose, H. et al.. 1.0μm n-Well CMOS/Bipolar Technology. IEEE Journal of Solid State Circuits SC-20(1):137–143, February, 1985.CrossRefGoogle Scholar
  19. [19]
    Ong, DeW.G. Modern MOS Technology. McGraw-Hill Book Co., 1984.Google Scholar
  20. [20]
    Parrillo, L.C. et al.. Twin-Tub CMOS — A Technology for VLSI Circuits. In IEEE Int. Electron Device Meeting. 1980.Google Scholar
  21. [21]
    Pattanayak, D.N. et al. Switching Conditions for CMOS Latch-Up Path with Shunt Resistances. IEEE Electron Device Letters EDL-4(4):116–119, April, 1983.CrossRefGoogle Scholar
  22. [22]
    Payne, R.S., W.N. Grant and W.J. Bertram. Elimination of Latch Up in Bulk CMOS. In Proc. of the international Electron Device Meeting, pages 248–251. IEEE, 1980.Google Scholar
  23. [23]
    Pinto, M.R. and R.W. Dutton. Accurate Trigger Condition Analysis for CMOS Latchup. IEEE Electron Device Letters EDL-6(2):100–102, February, 1985.CrossRefGoogle Scholar
  24. [24]
    Preckshot, N.E. et al.. Design Methodology of a 1.2-μm Double-Level-Metal CMOS Technology. IEEE Journal of Solid State Circuits SC-19(1):81–90, February, 1984.CrossRefGoogle Scholar
  25. [25]
    Soden, J.M., H.D. Stewart and R.A. Pastorek. ESD Evaluation of Radiation-hardened, High Reliability CMOS and MNOS ICs. In Proc. EOS/ESD Symposium, pages 134–146. Reliability Analysis Center, September, 1983.Google Scholar
  26. [26]
    Sugino, M., L.A. Akers and M.E. Rebeschini. Latchup-Free Schottky-Barrier CMOS. IEEE Trans, on Electron Devices: 110–118, 1983.Google Scholar
  27. [27]
    Sze, S.M. Physics of Semiconductor Devices. John Wiley & Sons, New York, 1969.Google Scholar
  28. [28]
    Sze, S.M. (ed.). VLSI Technology. McGraw-Hill Publishing Co., 1983.Google Scholar
  29. [29]
    Tanaka, S. et al.. A Subnanosecond 8K-Gate CMOS/SOS Gate Array. IEEE Journal on Solid State Circuits SC-19(5):657–662, October, 1984.CrossRefGoogle Scholar
  30. [30]
    Troutman, R.R. and H.P. Zappe. A Transient Analysis of Latchup in Bulk CMOS. IEEE Trans, on Electron Devices ED-30(2):170–179, February, 1983.CrossRefGoogle Scholar
  31. [31]
    Vittoz, E.A. MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology. IEEE Journal of Solid State Circuits SC-18(3):273–279, June, 1983.CrossRefGoogle Scholar
  32. [32]
    Walezyk, I. and J. Rubinstein. A Merged CMOS/Bipolar VLSI Process. In IEDM Technical Digest. December, 1983.Google Scholar
  33. [33]
    White, M.H. Characterization of CMOS Devices for VLSI. IEEE Journal of Solid-State Circuits SC-17(2):208–214, April, 1982.CrossRefGoogle Scholar
  34. [34]
    Wieder, A.W., C. Werner and J. Harter. Design Model for Bulk CMOS Scaling Enabling Accurate Latchup Prediction. IEEE Trans. on Electron Devices ED-30(3):240–245, March, 1983.CrossRefGoogle Scholar
  35. [35]
    Wu, C.Y. and M.Z. Lin. The Modified Bimos Dynamic RAM Cell Using LOCOS and N-Well Technologies. In Proc. of the International Symposium on VLSI Technology, Systems and Applications, pages 267–269. March, 1983.Google Scholar
  36. [36]
    Yamaguchi, T. et al.. Process and Device Performance of 1 μm-Channel n-Well CMOS Technology. IEEE Journal of Solid State Circuits SC-19(1):71–80, February, 1984.CrossRefGoogle Scholar

Copyright information

© Kluwer Academic Publishers 1986

Authors and Affiliations

  • Marco Annaratone
    • 1
  1. 1.Carnegie-Mellon UniversityPittsburghUSA

Personalised recommendations