Abstract
Functional approach to VLSI device testing has been advocated by several authors and various models have been proposed. Aim of this paper is to present functional testing as a methodology to test array of processors. An ordering criterion for instructions is presented, based upon considerations of observability and controllability of instructions independent from the array model adopted. Testing is performed by means of sequences of instructions. Necessary and sufficient conditions are introduced for definition of test sequences leading to optimum error coverage. Finally some criteria aiming to design test procedures are presented.
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References
M.A. Annaratone, M.G. Sami, “An Approach to functional testing of Microprocessors”, Proceedings of FTCS 12 (1982)
M.A. Annaratone, M.G. Sami, “Software Testing Technique for Universal Building Blocks of Multimicrosystems”, Proceedings of NCC (June 1982)
V. Cantoni, M. Ferretti, S. Levialdi, R. Stefanelli, “PAPIA: Pyramidal Architecture for Parallel Image Analysis”, in Proceedings of 7th Sysmposium on Computer Arithmetic, ed. IEEE, Urbana, IL (June 1985)
L. W. Fung, “MPPC: A massively parallel processing computer”, Goddard Space Flight Center Image Systems Section Rep. (Sept. 1976)
K. Hwang, F.A. Briggs, Computer Architecture and Parallel Processing, ed. McGraw-Hill Book Company
Yinghua Min, S.Y.H. Su, “Testing Functional Faults in VLSI”, in 19th Design Automation Conference, ed. IEEE, 1982.
Rosenfeld A . “Parallel Image Processing using Cellular Arrays”, IEEE Computer, vol. 16, n. 1 (1983)
H.J. Siegel, S.D. Smith, “Study of Multistage SIMD Interconnection networks”, Proc. 5th Annu. Symp. comput. Architecture, (April 1978)
T. Sridhar, D. S. Ho, T. J. Powell, S. M. Thatte, “Analysis and Simulation of Parallel Signature Analyzers”, in IEEE Test Conference, ed. IEEE (1982)
S.M. Thatte, J.A. Abraham, “Test generation for general microprocessors architectures”, Proc. FTCS-9(1979)
Williams T.W., “VLSI Testing”, in Computer, ed. IEEE (October 1984)
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© 1986 Plenum Press, New York
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Liotta, L., Sciuto, D. (1986). An Approach to Functional Testing of Array Processors. In: Cantoni, V., Levialdi, S., Musso, G. (eds) Image Analysis and Processing. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2239-9_6
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DOI: https://doi.org/10.1007/978-1-4613-2239-9_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-9312-5
Online ISBN: 978-1-4613-2239-9
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