Abstract
The design of a VLSI system typically involves many decisions relating to several levels of timing detail. Examples include choices relating to timing disciplines, architectural and circuit design paradigms, the number of clock phases, the number of amplification stages, the sizes of specific transistors, and the temporal behavior demanded of specific input signals (such as stability criteria they must obey). This paper discusses a framework for dealing with system timing issues in the context of very high level silicon compilers intended to aid in mapping abstract behavioral specifications into VLSI circuits. The paradigm considered allows the details of system timing to be gradually introduced as a design progresses. During the early stages of a design, no timing details need be explicit, and the only temporal constraints arise due to functionality, causality and stability criteria. As a design evolves, and decisions relating to resource allocation, computation schedules, timing and clocking disciplines are made, the temporal constraints on signals evolve correspondingly. If the external environment in which a system resides imposes any a priori temporal constraints, such constraints can be explicitly included in the initial specification, and accounted for in the synthesis process. The framework supports synchronous and asynchronous (self-timed) disciplines, multiphase-clocks, as well as techniques that bear on optimizations of performance metrics such as power and area.
May 1986, Revised
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References
Lusk, E.L and Ross A. Overbeek, The Automated Reasoning System ITP, Argonne National Laboratory, Argonne, IL (1984).
Subrahmanyam, P. A., “The Algebraic Basis of an Expert System for VLSI Design,” pp. 59–82 in Formal Aspects of VLSI Design, ed. G. Milne and P.A. Subrahmanyam, North-Holland, Amsterdam (1986).
Bryant, R., “A Switch-level model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, (February, 1984).
Davidson, S., Landskov, D, Shriver, B. D, and Mallett, P. W., “Some Experiments in local microcode compaction for horizontal machines,” IEEE Transactions on Computers C-30(7) pp. 460–477 (July 1981).
Fishburn, J.P. and A. E. Dunlop, TILOS: A Posynomial Programming Approach to Transistor Sizing, Proc. Inter. Conf. on Computer-Aided Design (November, 1985).
Hanna, F. and G.Daeche, “Specification and Verification Using Higher-Order Logic: A Case Study,” pp. 179–213 in Formal Aspects of VLSI Design, ed. G. Milne and P.A. Subrahmanyam, North-Holland, Amsterdam (1986).
Gordon, M., “Why Higher-Order Logic is a good formalism for specifying and verifying hardware,” pp. 153–178 in Formal Aspects of VLSI Design, ed. G. Milne and P.A. Subrahmanyam, North-Holland, Amsterdam (1986).
Hayes, A.B., “Stored State Asynchronous Sequential Circuits,”IEEE Trans, on Computers C-30 pp. 596–600 (August 1981).
Horn, David, Personal communication. 1986.
Smith, R.J. II, “Fundamentals of Parallel Logic Simulation,” Proc. of 2Srd Design Automation Conference, pp. 2–11 (June 1986).
Krambeck, R.H., Charles M. Lee and H-F. S Law, “High-Speed Compact Circuits with CMOS,” IEEE Journal of Solid-State Circuits SC-17(3) pp. 614–619 (June 1982).
Goncalves, N.F., and Hugo J. De Man, “NORA: A Race free Dynamic CMOS Technique for Pipelined Logic Structures,” IEEE Journal of Solid-State Circuits SC-18(3) pp. 261–266 (June 1983).
G. De Micheli and A. Sangiovanni-Vincentelli, “Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications,” IEEE Transactions on CAD, (July 1983).
Mishra, B. and E. Clarke, “Automatic and hierarchical verification of asynchronous circuits using temporal logic,” Technical Report CMU- CS-83–155, Dept. of Computer Science, CMU (September 1983).
Moszkowski, B., “A temporal logic for multilevel reasoning about hardware,” IEEE Computer 18(2) pp. 10–19 (February 1985).
Nagel, L., SPICE2: A Computer Program to Simulate Semiconductor Circuits, Electronics Research Laboratory, University of California, Berkeley (1975).
Orton, D.W.R., Clocked Dynamic Logic for CMOS, Racal Research Internal Memo, Worton Drive, Worton Grange Industrial Est., Reading RG2 OSB, England (January 1984).
Marple, David P., Performance Optimization of Digital VLSI Circuits,Technical Report CSL-TR-86–308, Stanford University (October 1986).
P. Quinton, The Systematic Design of Systolic Arrays, IRISA Technical Report (May 1983).
Subrahmanyam, P. A. and S. Purushothaman, “An Algebraic Basis for Specifying and Reasoning about Protocols For Designing Self Timed Circuits,” pp. 133–144 inVLSI Design of digital systems, ed. F. Anceau and E.J. Aas, North Holland (1983).
Seitz, C., “Self Timed Systems,” Caltech Conference on VLSI, (1980).
Subrahmanyam, P.A., “Synapse: An Expert System for VLSI Design,” IEEE Computer 19(7) pp. 78–89 (July 1986).
Sutherland, Ivan, Personal communication. 1986.
Sutherland, Ivan, A Theory of Logical Effort, SSA 4679, Sutherland, Sproull and Associates, Inc. (1986).
Szymanski, T.G.,LEADOUT: A Static Timing Analyzer for MOS Circuits, Proc. Inter. Conf. on Computer-Aided Design (November, 1986).
Weste, N. and Esraghian, K., Principles of CMOS VLSI Design: A Systems Perspective, Addison-Wesley, Ma. (1985).
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© 1988 Kluwer Academic Publishers, Boston
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Subrahmanyam, P.A. (1988). Towards a framework for dealing with system timing in Very High Level Silicon Compilers. In: Birtwistle, G., Subrahmanyam, P.A. (eds) VLSI Specification, Verification and Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 35. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2007-4_5
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DOI: https://doi.org/10.1007/978-1-4613-2007-4_5
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