Verification of Asynchronous Circuits: Behaviors, Constraints and Specifications
An algebraic methodology based on Characteristic Functions (CFs) and allowing to compare switch-level circuits with higher-level specifications is presented.
Switch-level networks, ‘user’ behaviors, input constraints and specifications are modelled as asynchronous automata which form a Boolean algebra.
Machine composition corresponds to the product of the Boolean algebra. Internal variables can be abstracted, and more generally, a component automaton can be reduced by projection under the presence of a local domain constraint. The constraints are validated by comparison with the actual user of each component
Formal verification implies comparison with a high-level specification which may either be complete or consists of a collection of properties. Verification of safety and liveness with respect to a property reduces to the validation of Boolean inequalities.
This methodology is applied to a new structure of mutual exclusion ensuring fairness.
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