Abstract
A specific design style is only ever used if it meets the required needs of the task in hand. The task in hand now is that of generating large, complex, application specific systems on silicon in a fairly short space of time with the confidence that they will perform to the required specification. In the past the development of a large circuit might have been done using a team of engineers over a period of few years, e.g. the development of the 68000 microprocessor. This method of circuit development is not acceptable in the present day due to the time and manpower spent in iterating to get the design correct. What is needed is a design technique which is easy to follow and gives very high degree of confidence in the first time correct implementation of the circuit.
The author is jointly funded by the British Science and Engineering Research Council, and Racal Research based in Reading, England.
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References
Randal Everitt Bryant “A Switch-Level Simulation Model for Integrated Logic Circuits,” PhD. Thesis, also available as a Technical Report MIT/LCS/TR-259, Laboratory for Computer Science, MIT, Massachusetts, March 1981.
A. Camilleri, M. Gordon and T. Melham “Hardware Verification using Higher-Order Logic,” In: Proceedings of the IFIP International Conference: From H.D.L. Descriptions to Guaranteed Correct Circuit Designs, Grenoble, September 9–11, 1986.
I. S. Dhingra Ph.D. Thesis. Computer Laboratory, University of Cambridge. 1987
Nelson F. Goncalves and Hugo J. De Man “NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures,” IEEE Journal of Solid-State Circuits, SC-18 (3), June 1983 pp. 261–266.
M. J. C. Gordon “hol: A Machine Oriented Formulation of Higher-Order Logic,” Technical Report 68, Computer Laboratory, University of Cambridge, 1985.
M. J. C. Gordon “Why Higher-Order Logic is a Good Formalism for Specifying and Verifying Hardware,” In: Formal Aspects of VLSI Design, edited by G. Milne and P. A. Subrahmanyam, North-Holland, 1986.
R. H. Krambeck, Charles M. Lee and Hung-Fai Stephen Law “High-Speed Compact Circuits with CMOS,” IEEE Journal of Solid-State Circuits, SC-17 (3), June 1982 pp. 614–619.
D. W. R. Orton “Clocked Dynamic Logic for CMOS,” Racal Research Internal Memo of 10th January 1984, Worton Drive, Worton Grange Industrial Est., Reading RG2 OSB, England.
Glynn Winskel “Models and Logic of MOS Circuits,” in VLSI Specification, Verification and Synthesis, Ed. G. Birtwistle and P.A. Subrahmanyam, Kluwer 1987. (These proceedings)
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© 1988 Kluwer Academic Publishers, Boston
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Dhingra, I.S. (1988). Formal Validation of an Integrated Circuit Design Style. In: Birtwistle, G., Subrahmanyam, P.A. (eds) VLSI Specification, Verification and Synthesis. The Kluwer International Series in Engineering and Computer Science, vol 35. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-2007-4_10
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DOI: https://doi.org/10.1007/978-1-4613-2007-4_10
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