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Overview of the IDA System: A Toolset for VLSI Layout Synthesis

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VLSI CAD Tools and Applications

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 24))

Abstract

The Integrated Design Aides (IDA) toolset is a set of VLSI CAD software programs that have been developed to make the most effective use possible of a designer’s time. IDA incorporates a number a layout synthesis tools capable of generating both structured circuits, such as ALU’s, and random logic. The system centers around a constraint-based, symbolic language called IMAGES and a compacter methodology. This paper describes IDA, its capabilities, techniques, and status.

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References

  1. Ackland, B., A. Dunlop, J. Fishburn, D. Hill K. Keutzer. H. Moscovitz, J. Tauke, “The IMAGES Symbolic Layout Language: Version 0.0.” AT&T Bell Labs internal memorandum, (1985).

    Google Scholar 

  2. Ackland, B., N. Weste, “An Automatic Assembly Tool for Virtual-Grid Symbolic Layout,” Proceedings of VLSI 83, 457–466, (1983).

    Google Scholar 

  3. Bryant, R. E., MOSSIM: A Logic-Level Simulator for MOS LSI, User’s Manual, Integrated Circuit Memo 80–21, M.I.T. Department of EECS. 1980.

    Google Scholar 

  4. Chu, K-C., J. P. Fishburn, P. Honeyman. Y. E. Lien, “Vdd - A VLSI Design Database System,” Proceedings of the 1983 Annual Meeting -- Database Week, IEEE Computer Society Press, 1983.

    Google Scholar 

  5. Hill, D. D., “Edisim -- A Graphical Simulator Interface for LSI Design,” IEEE Transactions on Computer Aided Design of Integrated Circuits, April 1983.

    Google Scholar 

  6. Fishburn, J. P, and A. Dunlop, TILOS: A Posynomial Approach to Transistor Sizing, Proceedings of IEEE International Conference on Computer-Aided Design-85, Santa Clara, Ca. 1985.

    Google Scholar 

  7. Hill, D., “ICON: A Tool for Design at Schematic, Virtual-Grid and Layout Levels,” IEEE Design and Test, Vol. 1, 4, 53–61 (1984).

    Article  Google Scholar 

  8. Hill, D., “CAD Systems for VLSI Design” Proceedings of the National Communications Forum Rosemont, September 84, 673–691.

    Google Scholar 

  9. Hill, D., “SC2: A Hybrid Automatic Layout Program,” Proceedings International Conference on Computer Aided Design. Santa Clara, November 85, 172–174.

    Google Scholar 

  10. Hsueh, Min-Yu. Symbolic Layout and Compaction of Integrated Circuits. PhD thesis,. University of California at Berkeley. December. 1979.

    Google Scholar 

  11. Hill, D., J. Fishburn. M. Leland. “Effective Use of Virtual-Grid Compaction in Macro- Module Generators.” Proceedings 22nd Design Automation Conference. Las Vegas. June 85. p. 172–174.

    Google Scholar 

  12. Johnson. D., “Efficient Algorithms for Shortest Paths in Sparse Networks,” Journal of the ACM, Vol. 24. 1, 1977.

    Article  MATH  Google Scholar 

  13. Johnson. S., “Hierarchical Design Validation Based on Rectangles.” Proceedings Conference on Advanced Research in VLSI. M.I.T., p. 97–100. January 1982.

    Google Scholar 

  14. Kernighan, B.W and S. Lin. “An Efficient Heuristic Procedure for Partitioning Graphs.” Bell Sys. Tech. Journal, Vol. 49 (2), pp. 291–308., 1970. Solving Equalities, Inequalities and Shortest Paths, in preparation, 1986.

    MATH  Google Scholar 

  15. Keutzer, K., Solving Equalities, Inequalities and Shortest Paths, in preparation. 1986.

    Google Scholar 

  16. Lengauer. T., “On the Solution of Inequality Systems Relevant to IC-Layout.” Journal of Algorithms, 5, p. 408–421. 1984.

    Article  MathSciNet  MATH  Google Scholar 

  17. Lengauer, T., K. Mellhorn, “The HILL System: A Design Environment for the Hierarchical Specification, Compaction, and Simulation of Integrated Circuit Layouts.” Proceedings 1984 Conference on Advanced Research in VLSI, M.I.T., p. 139–147. 1983.

    Google Scholar 

  18. Lipton, R., S. North, R. Sedgewick, J. Valdes, G. Vijayan, “ALI: A Procedural Language to Describe VLSI Circuits,” Proceedings 19th Design Automation Conference. p. 467–474. 1983.

    Google Scholar 

  19. R. Lipton, J. Valdes, G. Vijayan, S. North, R. Sedgevvick, “VLSI Layout as Programming,” ACM Transactions on Programming Languages and Systems, Vol 5, no. 3, 1983.

    Google Scholar 

  20. Liao. Y-Z., C. Wong, “An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints.” IEEE Trans, on Computer Aided Design of Integrated Circuits and Systems, CAD-2, 2, p. 62–69, 1983.

    Article  Google Scholar 

  21. Lopez, A.D., and H-F. Law, “A Dense Gate-Matrix Layout Method for MOS VLSI,” IEEE Transactions of Electron Devices, Vol. ED-27, No 8, Aug 1980.

    Google Scholar 

  22. Matheson, T., C. Christensen, M. Buric, “A Software Environment for Building Core- Microcomputer Compilers,” Proceedings International Conference on Computer Design, p. 221–224, 1985.

    Google Scholar 

  23. Montiero da Mata, J., “ALLENDE: A Procedural Language for the Hierarchical Specification of VLSI Layout,” Proceedings 22nd Design Automation Conference. p. 183–189, 1985.

    Google Scholar 

  24. Nagel, L. W., “ADVICE of Circuit Simulation,” IEEE Symp. on Computers and Systems, 1980, Houston, TX.

    Google Scholar 

  25. Nagel, L. W., SPICE2 - A Computer Program to Simulate Semiconductor Circuits, University of California, Berkeley, ERL Memorandum Number ERL-M520. May. 1975.

    Google Scholar 

  26. Reichelt, M., Improved Abstractions for Hierarchical Constraint-Graph Compaction, Master’s thesis. M.I.T., September, 1986.

    Google Scholar 

  27. Rosenberg. J., “Chip Assembly Techniques for Custom IC Design in a Symbolic Virtual- Grid Environment.” Proceedings Conference on Advanced Research in VLSI. M.I.T., p. 213–217. January, 1984.

    Google Scholar 

  28. Szymanski. T. unpublished memorandum, 1982.

    Google Scholar 

  29. Szymanski, T., C. J Van Wyk. “Space Efficient Algorithms for VLSI Artwork Analysis.” Proceedings of the 20th Design Automation Conference, Miami, pp. 734–739. 1983.

    Google Scholar 

  30. Tarjan. R.,“On the Efficiency of a Good but Non-Linear Set Union Algorithm,” Journal of the ACM. Vol. 22. 2, (1975).

    Article  MathSciNet  Google Scholar 

  31. Ullman, J. D., Computational Aspects of VLSI, Computer Science Press. Rockville MD, 1984.

    MATH  Google Scholar 

  32. Weste. N., “Virtual Grid Symbolic Layout,” Proceedings of the 18th Design Automation Conference, Nashville. Tenn., 1981.

    Google Scholar 

  33. Wolf, W., “An Experimental Comparison of 1-D Compaction Algorithms.” Chapel Hill Conference on VLSI, Computer Science Press, Rockville MD. Henry Fuchs. May. 1985.

    Google Scholar 

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Author information

Authors and Affiliations

  1. AT&T Bell Labs, Murray Hill, New Jersey, USA

    Dwight D. Hill, Kurt Keutzer & Wayne Wolf

Authors
  1. Dwight D. Hill
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  2. Kurt Keutzer
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  3. Wayne Wolf
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Editor information

Editors and Affiliations

  1. Institute for Integrated Systems, Swiss Federal Institute of Technology, Zurich, Switzerland

    Wolfgang Fichtner  & Martin Morf  & 

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© 1987 Kluwer Academic Publishers

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Hill, D.D., Keutzer, K., Wolf, W. (1987). Overview of the IDA System: A Toolset for VLSI Layout Synthesis. In: Fichtner, W., Morf, M. (eds) VLSI CAD Tools and Applications. The Kluwer International Series in Engineering and Computer Science, vol 24. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1985-6_8

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  • DOI: https://doi.org/10.1007/978-1-4613-1985-6_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-9186-2

  • Online ISBN: 978-1-4613-1985-6

  • eBook Packages: Springer Book Archive

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