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Fault Tolerant VLSI Multicomputers

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VLSI CAD Tools and Applications

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 24))

Abstract

An approach is presented to increasing the reliability of future high-end systems beyond what is possible with technological solutions alone. The system consists of computation nodes and communication nodes, interconnected by high-speed dedicated links. These components are relied upon to detect errors while system level protocols are used for error recovery and reconfiguration. The use of duplication and matching for implementing the self-checking nodes allows us to restrict a detailed analysis of the impact of all possible faults to the comparator, a circuit that can be implemented in a relatively straight-forward way in NMOS or CMOS technology.

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Author information

Author notes

  1. Yuval Tamir

    Present address: Computer Science Dept., University of California, Los Angeles, CA, 90024, USA

Authors and Affiliations

  1. Computer Science Division Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 94720, USA

    Carlo H. Séquin & Yuval Tamir

Authors
  1. Carlo H. Séquin
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  2. Yuval Tamir
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Editor information

Editors and Affiliations

  1. Institute for Integrated Systems, Swiss Federal Institute of Technology, Zurich, Switzerland

    Wolfgang Fichtner  & Martin Morf  & 

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© 1987 Kluwer Academic Publishers

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Séquin, C.H., Tamir, Y. (1987). Fault Tolerant VLSI Multicomputers. In: Fichtner, W., Morf, M. (eds) VLSI CAD Tools and Applications. The Kluwer International Series in Engineering and Computer Science, vol 24. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1985-6_15

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  • DOI: https://doi.org/10.1007/978-1-4613-1985-6_15

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-9186-2

  • Online ISBN: 978-1-4613-1985-6

  • eBook Packages: Springer Book Archive

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