Architecture of Modern VLSI Processors

  • Priscilla M. Lu
  • Don E. Blahut
  • Kevin S. Grant
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 24)


In recent years, the focus of VLSI architecture effort has been primarily on the tradeoffs possible in new microprocessor instruction sets. The result has been a collection of machines with new streamlined instruction sets, and new hardware subsystems tuned to maximize performance. This leaves many designers with a difficult problem: how to apply these new ideas within the constraints of an existing instruction set. Moreover, as the industry converges on faster internal architectures for microprocessors, the design problem changes to address more system-level issues, such as caching structures, I/O, memory interfaces. and peripherals. Traditionally, it has been difficult to analyze these system-level issues in detail, and as a result, many machines have been built based on intuition or incomplete data. However, the availability of existing microprocessors, and rapid advances in CAD techniques, have made possible experiments that help guide design decisions with more solid data.


Register File Data Cache Pipeline Stage Instruction Cache Execution Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Patterson D., “Reduced Instruction Set Computers”, CACM Vol.28 No.1, January 1985, p.8–21.Google Scholar
  2. 2.
    Patterson D. A., and C. Sequin, “A VLSI RISC,” Computer, Vol. 15, 9 (Sept. 1982) p.8–21.CrossRefGoogle Scholar
  3. 3.
    Moussouris J., et al., “A CMOS RISC Processor with Integrated System Functions - The MIPS Microprocessor,” Spring COMPCON ’86, p, 126–131.Google Scholar
  4. 4.
    Birnbaum J. S., W. S. Worley, “Beyond RISC: High-Precision Architecture - The Next Generation of HP Computers: The Spectrum Program,” Spring COMPCON’86, p. 40–47.Google Scholar
  5. 5.
    Radin G., “The 801 Minicomputer”, IBM Journal of Research and Development, Vol 27, 3, May 1983, p. 237–246.MathSciNetCrossRefGoogle Scholar
  6. 6.
    Campbell S. T., “MAC-8 Microprocessor Summary”, MACS Systems Designer’s Handbook, Bell Laboratories, March 8, 1976.Google Scholar
  7. 7.
    Nelson M. S., B. Ng, W. Wu, “Architecture of the WE32200 Chip Set” COMPCON ’87Spring Google Scholar
  8. 8.
    Ditzel D., R. McLellan, “Register Allocation For Free: The C Machine Stack Cache,” Proceedings Symposium on Architecture Support for Programming Languages and Operating Systems March, 1982, p.48–56.Google Scholar
  9. 9.
    Lee J. K. F., A. Smith, “Branch Prediction Strategies and Branch Target Buffer Design,” Computer, Vol 17, No. 1 (January 1984), p.6–22.CrossRefGoogle Scholar
  10. 10.
    P. M. Lu, et al., “Architecture of a VLSI MAP for BELLMAC-32 Microprocessor”, COMPCON Spring 83, p213–217.Google Scholar
  11. 11.
    IBM Personal Computer Technology Handbook, 1986.Google Scholar

Copyright information

© Kluwer Academic Publishers 1987

Authors and Affiliations

  • Priscilla M. Lu
    • 1
  • Don E. Blahut
    • 1
  • Kevin S. Grant
    • 1
  1. 1.AT&T Information SystemsHolmdelUSA

Personalised recommendations