Abstract
As the complexity of VLSI devices increases, so does the need to rely on computer aided design (CAD) methods. As VLSI designs grow they push the limits of the CAD tools, and in some cases require new approaches to design and verification. This paper reports on experiences with a particular approach taken to design a 170,000 transistor single chip CMOS microprocessor. The chip was an implementation of the Bell Labs C-Machine 1, 2 architecture, code-named CRISP (C-Machine Reduced Instruction Set Processor) during its design. The major design tools used are described along with pleasant and unpleasant surprises in their use. Problems with more traditional approaches due to the increased size of designs are discussed.
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References
D. R. Ditzel and H. R. McLellan, “Register Allocation for Free: The C Machine Stack Cache,” Proc. of Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, California, pp. 48–56 (March 1982).
D. D. Hill, “An Analysis of C Machine Support for Other Block Structured Languages,” Computer Architecture News 11(4), pp. 6–16 (September 1983).
B. W. Kernighan and D. M. Ritchie, The C Programming Language, Prentice-Hall (1978).
A. G. Fraser, “Circuit Design Aids,” The Bell System Technical Journal 57(6, Part 2), pp. 2233–2249 (July-August 1978).
N. H. E. Weste, “MULGA - An Interactive Symbolic Layout System for the Design of Integrated Circuits,” The Bell System Technical Journal 60(6, part 1), pp. 823–857 (July-August 1981).
N. H. E. Weste, “Virtual Grid Symbolic Layout,” Proceedings of the 18th Design Automation Conference, pp. 225–233. (June 1981).
N. Weste and B. Ackland, “A Pragmatic Approach to Topological Symbolic IC Design,” Proceedings of the 1st International Conference on VLSI, Edinburgh UK, pp. 117–129 (August 1981).
B. Ackland and N. Weste, “An Automatic Assembly Tool for Virtual Grid Symbolic Layout,” Proceedings of the 2nd International Conference on VLSI, Trondhiem Norway, pp. 457–466. (August 1983).
T. G. Szymanski and C. J Van Wyk, “Goalie: A Space Efficient System for VLSI Artwork Analysis,” IEEE Design & TEST 2(3), pp. 64–72 (June, 1985).
C. Ebeling and O. Zajicek, Validating VLSI Circuit Layout by Wirelist Comparison, Proceedings of the Design Automation Conference (1983), pp. 172–173.
L. W. Nagel, “ADVICE for Circuit Simulation,” Proceedings of the 1980 Symposium on Circuits and Systems (April 28, 1980).
L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, University of California, Berkeley (May 1975).
B. R. Chawla, H. K. Gummel, and P. Kozak, “MOTIS - An MOS Timing Simulator,” IEEE Transactions on Circuits and Systems 22(12) (December, 1975).
T. G. Szymanski, “LEADOUT: A Static Timing Analyzer for MOS Circuits,” Proceedings of the ICCAD Conference (October 1986).
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© 1987 Kluwer Academic Publishers
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Ditzel, D.R., Berenbaum, A.D. (1987). Experience with CAD Tools for a 32-Bit VLSI Microprocessor. In: Fichtner, W., Morf, M. (eds) VLSI CAD Tools and Applications. The Kluwer International Series in Engineering and Computer Science, vol 24. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1985-6_11
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DOI: https://doi.org/10.1007/978-1-4613-1985-6_11
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-9186-2
Online ISBN: 978-1-4613-1985-6
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