Gate Matrix Layout
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In this chapter, we consider the layout of MOS circuits in the style of Gate Matrix. This layout style was introduced by Lopez and Law [LoLa80] in 1980 for the layout of custom CMOS circuits. It is very similar to other one-dimensional layout styles, such as Weinberger arrays, that were studied in [Wein67, OhMK79, KaFu79]. Since it uses a very simple and regular structure, this layout style greatly simplifies the layout procedure. It is also adaptable to a team effort and can accommodate changes in the design or design rules. Various algorithms for the Gate Matrix layout problem have been developed [LoLa80, Wing82, Wing83, Li83, WiHW85]. These algorithms are based on an earlier algorithm by Ohtsuki et al [OhMK79] for the One-Dimensional Logic Assignment Problem.
KeywordsSimulated Annealing Simulated Annealing Algorithm Layout Problem VLSI Design Dynamic Binding
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