PLA Folding

  • D. F. Wong
  • H. W. Leong
  • C. L. Liu
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 42)


Programmable Logic Arrays (PLA’s) are structured logic arrays which implement multiple output combinational logic functions. They are perhaps the most popular circuit modules that implement two-level logic functions. In general, a PLA can be described in symbolic form by a matrix called personality matrix. Most personality matrices are very sparse. Consequently, a direct implementation of a PLA will result in a rather significant waste of chip area. Such waste will reduce circuit yield and degrade time performance of the PLA. PLA folding [HaNS82, DeSa83, LeLi84, WoLL87] is a general technique to reduce the total area of a PLA. By a simple folding of the columns of a PLA, we mean to let two input variables or two output functions share one column. In a multiple folding of the columns of a PLA, we allow two or more input variables or two or more output functions to share one column. It is customary to disallow an input variable and an output function to share the same column. For the PLA in Fig.6.1(a), Fig.6.1(b) shows a simple folding of the columns and Fig.6.1(c) shows a multiple folding of the columns of the PLA.


Cost Function Simulated Annealing Product Term Output Line VLSI Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1988

Authors and Affiliations

  • D. F. Wong
    • 1
  • H. W. Leong
    • 2
  • C. L. Liu
    • 3
  1. 1.University of Texas at AustinUSA
  2. 2.National University of SingaporeSingapore
  3. 3.University of Illinois at Urbana-ChampaignUSA

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