Wafer-Level Integrated Systems pp 245-279 | Cite as

# Function-Specific Testing

## Abstract

The previous chapter emphasized general purpose testing schemes for combinational and sequential logic circuits. This chapter describes several special-purpose testing schemes. Three distinct circuit functions (memory arrays, regular logic arrays and programmable logic arrays) are used as examples of the various techniques which can be used. A major issue for special purpose testing is reduction of the size of the set of test vectors, drawing on the structure of the specific function being considered. Similar reductions in the size of tests for wafer-scale integrated circuits will also be important and the commonly used regularity of such wafer-scale functions suggests that distributed testing, conducted in parallel on regions of the array which do not interact through faults, will be possible. Given the set of test vectors, and regions which can be concurrently tested, the actual generation, routing and response analysis of test vectors can be implemented using the general purpose testing structures (e.g. scan path testing, response compression, TMR, etc.) discussed in the previous chapter. The techniques discussed below begin with testing of memory arrays, where the contents of each individual cell (storage site) can be directly viewed at the memory array’s primary output. Next, testing of regular logic arrays is considered. In this case, the regular structure is qualitatively similar to that of the memory array but the responses of internal cells (e.g. accumulator cells) are not directly observable at the array’s primary outputs. Design of the test must then propagate those responses, without modification, through the array to the primary outputs.

### Keywords

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