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Architectural Yield Optimization

  • N. R. Strader
  • J. C. Harden

Abstract

Fabrication of integrated circuits or systems that span an entire wafer or a significant part of a wafer have held the interest of a number of semiconductor researchers [1]. The expected benefits of smaller size, increased reliability, reduced cost, shorter signal delays, and simpler packaging are significant. Unfortunately, most of the previously reported attempts have been surpassed by increased density, improved circuitry, and better packaging of conventional integrated circuits.

Keywords

Binary Tree Poisson Model Negative Binomial Model Yield Enhancement Node Method 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1989

Authors and Affiliations

  • N. R. Strader
  • J. C. Harden

There are no affiliations available

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