## Abstract

Fabrication of integrated circuits or systems that span an entire wafer or a significant part of a wafer have held the interest of a number of semiconductor researchers [1]. The expected benefits of smaller size, increased reliability, reduced cost, shorter signal delays, and simpler packaging are significant. Unfortunately, most of the previously reported attempts have been surpassed by increased density, improved circuitry, and better packaging of conventional integrated circuits.

### Keywords

Hexagonal Expense Pyramid Lawson Fiberglass## Preview

Unable to display preview. Download preview PDF.

### References

- [1]N. R. Strader and J. S. Kilby, “Wafer Scale Integration — Historical Perspective,” Semiconductor Research Corporation Workshop, Wafer Scale Integration: An Assessment, September, 1984.Google Scholar
- [2]R. L. Petritz, “Current State of Large Scale Integration Technology,” Proceedings of the Fall Joint Computer Conference, pp. 65–85, 1967.Google Scholar
- [3]R. C. Aubusson and I. Catt, “Wafer-Scale Integration — A Fault-Tolerant Procedure,” IEEE Journal of Solid-State Circuits, vol. SC-13, pp. 339–344, 1978.CrossRefGoogle Scholar
- [4]D. F. Calhoun, “The Pad Relocation Technique for Interconnecting LSI Arrays of Imperfect Yield,” Proceedings of the Fall Joint Computer Conference, pp. 99–109, 1969.Google Scholar
- [5]F. B. Manning, “An Approach to Highly Integrated, Computer-Maintained Cellular Arrays,” IEEE Transactions on Computers, vol. C-26, pp. 536–552, 1977.CrossRefGoogle Scholar
- [6]F. R. K. Chung, F. T. Leighton, and A. L. Rosenberg, “Diogenes: A Methodology for Designing Fault-Tolerant VLSI Processor Arrays,” Proceedings of the 13th International Symposium on Fault-Tolerant Computing, pp. 26–32, 1983.Google Scholar
- [7]A. L. Rosenberg, “The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors,” IEEE Transactions on Computers, vol. C-32, pp. 902–910, 1983.CrossRefGoogle Scholar
- [8]T. E. Mangir and A. Avizienis, “Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs,” IEEE Transactions on Computers, vol. C-31, pp. 609–615, 1982.CrossRefGoogle Scholar
- [9]T. E. Mangir, “Use of On-Chip Redundancy for Fault-Tolerant VLSI Design,” UCLA Computer Science Department, Report CSD-820201, February, 1982.Google Scholar
- [10]K. S. Hedlund, “Wafer Scale Integration of Parallel Processors,” Ph.D. dissertation, Purdue University, December, 1982.Google Scholar
- [11]K. S. Hedlund, “WASP — WAfer-scale Systolic Processor,” VLSI Design, pp. 70–71, July/August, 1983.Google Scholar
- [12]J. E. Price, “A New Look at Yield of Integrated Circuits,” Proceedings of the IEEE, vol. 58, pp. 1290–1291, 1970.CrossRefGoogle Scholar
- [13]T. Leighton and C. E. Leiserson, “Wafer-Scale Integration of Systolic Arrays,” IEEE Transactions on Computers, vol. C-34, pp. 448–461, 1985.CrossRefGoogle Scholar
- [14]J. I. Raffel, A. H. Anderson, G. H. Chapmann, S. L. Garverick, K. H. Konkle, B. Mathur, and A. M. Soares, “A Demonstration of Very Large Area Integration Using Laser Restructuring,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 781–784, May, 1983.Google Scholar
- [15]J. I. Raffel, A. H. Anderson, G. H. Chapmann, K. H. Konkle, B. Mathur, A. M. Soares, and P. W. Wyatt, “A Wafer-Scale Digital Integrator Using Restructurable VLSI,” IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 399–406, 1985.CrossRefGoogle Scholar
- [16]C. Brown, “Researchers Attempt Wafer-Scale Integration,” Electronic Engineering Times, September 12, 1983.Google Scholar
- [17]D. L. Peltzer, “Wafer-Scale Integration: The Limits of VLSI?,” VLSI Design, pp. 43–47, September, 1983.Google Scholar
- [18]“Trilogy Ltd. Closes Semiconductor Line, Halves Work Force,” Wall Street Journal, vol. 74, p. 5, August 10, 1984.Google Scholar
- [19]C. H. Stapper, A. N. McLaren, and M. Dreckmann, “Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partial Good Product,” IBM Journal of Research and Development, vol. 24, pp. 398–409, 1980.CrossRefGoogle Scholar
- [20]C. H. Stapper and R. J. Rosner, “A Simple Method for Modeling VLSI Yields,” Solid State Electronics, vol. 25, pp. 487–489, 1982.CrossRefGoogle Scholar
- [21]C. H. Stapper, R. P. Castrucci, R. A. Maeder, W. E. Rowe, and R. A. Verhelst, “Evolution and Accomplishments of VLSI Yield Management at IBM,” IBM Journal of Research and Development, vol. 26, pp. 532–544, 1982.CrossRefGoogle Scholar
- [22]C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated Circuit Yield Statistics,” Proceedings of the IEEE, vol. 71, pp. 453–470, 1983.CrossRefGoogle Scholar
- [23]C. H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,” IBM Journal of Research and Development, vol. 27, pp. 549–557, 1983.CrossRefGoogle Scholar
- [24]C. H. Stapper, “Modeling of Defects in Integrated Circuit Photolithographic Patterns,” IBM Journal of Research and Development, vol. 28, pp. 461–474, 1984.CrossRefGoogle Scholar
- [25]D. M. Stewart, “The Economics of Laser Repairing the One Megabit Dynamic RAM,” SEMICON/West, May, 1984.Google Scholar
- [26]D. M. Stewart, “Lasers Fix Dynamic RAMs,” Electronics Week, vol. 58, no. 5, pp. 45–49, February 4, 1985.Google Scholar
- [27]J. F. M. Bindels, J. D. Chilpala, F. H. Fischer, T. F. Mantz, R. G. Nelson, and R. T. Smith, “Cost-Effective Yield Improvement in Fault-Tolerant VLSI Memory,” IEEE International Solid-State Circuits Conference Digest, pp. 82–83, 1981.Google Scholar
- [28]K. Kokkonen, P. O. Sharp, R. Albers, J. Dishaw, F. Louie, and R. J. Smith, “Redundancy Techniques for Fast Static RAMs,” IEEE International Solid-State Circuits Conference Digest, pp. 80–81, 1981.Google Scholar
- [29]B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” Proceedings of the IEEE, vol. 52, pp. 1537–1545, 1964.CrossRefGoogle Scholar
- [30]B. T. Murphy, “Comments on ‘A New Look at Yield of Integrated Circuits’,” Proceedings of the IEEE, vol. 59, p. 1128, 1971.CrossRefGoogle Scholar
- [31]R. B. Seeds, “Yield, Economic, and Logistic Models for Complex Digital Arrays,” IEEE International Convention Record, Part 6, pp. 60–61, 1967.Google Scholar
- [32]W. G. Ansley, “Computation of Integrated-Circuit Yields from the Distribution of Slice Yields for the Individual Devices,” IEEE Transactions on Electron Devices, vol. ED-15, pp. 405–406, 1968.CrossRefGoogle Scholar
- [33]G. E. Moore, “What Level of LSI is Best for You?,” Electronics, vol. 43, pp. 126–130, February, 1970.Google Scholar
- [34]T. Okabe, M. Nagata, and S. Shimada, “Analysis on Yield of Integrated Circuits and a New expression for the Yield,” Electrical Engineering in Japan, vol. 92, pp. 135–141, December, 1972.CrossRefGoogle Scholar
- [35]R. M. Warner, Jr., “Applying a Composite Model to the IC Yield Problem,” IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 86–95, 1974.CrossRefGoogle Scholar
- [36]R. M. Warner, Jr., “A Note on IC-Yield Statistics,” Solid-State Electronics, vol. 24, pp. 1045–1047, 1981.CrossRefGoogle Scholar
- [37]C. H. Stapper, “Defect Density Distribution for LSI Yield Calculations,” IEEE Transactions on Electron Devices, vol. ED-20, pp. 655–657, 1973.CrossRefGoogle Scholar
- [38]C. H. Stapper, “On a Composite Model to the IC Yield Problem,” IEEE Journal of Solid-State Circuits, vol. SC-10, pp. 537–539, 1975.CrossRefGoogle Scholar
- [39]C. H. Stapper, “LSI Yield Modeling and Process Monitoring,” IBM Journal of Research and Development, vol. 20. pp. 228–234, 1976.CrossRefGoogle Scholar
- [40]C. H. Stapper, “Comments on ‘Some Considerations in the Formulation of IC Yield Statistics’,” Solid State Electronics, vol. 24, pp. 127–132, 1981.CrossRefGoogle Scholar
- [41]C. H. Stapper, “Yield Model for 256K RAMs and Beyond,” IEEE International Solid-State Circuits Conference Digest, pp. 12–13, 1982.Google Scholar
- [42]A. B. Glaser and G. E. Subak-Sharpe, Integrated Circuit Engineering, Reading, MA: Addison-Wesley, 1979.Google Scholar
- [43]S. M. Hu, “Some Considerations in the Formulation of IC Yield Statistics,” Solid-State Electronics, vol. 22, pp. 205–211, 1979.CrossRefGoogle Scholar
- [44]A. Rogers, Statistical Analysis of Spatial Dispersions, London: Pion, Ltd., pp. 12–20, 1974.Google Scholar
- [45]R. S. Hemmert, “Poisson Process and Integrated Circuit Yield Predictions,” Solid-State Electronics, vol. 24, pp. 511–515, 1981.CrossRefGoogle Scholar
- [46]O. Paz, and T. L. Lawson, “Modification of Poisson Statistics: Modeling Defects Induced by Diffusion,” IEEE Journal of Solid-State Circuits, vol. SC-12, pp. 540–546, 1977.CrossRefGoogle Scholar
- [47]A. Gupta and J. A. Lathrop, “Yield Analysis of Large Integrated-Circuit Chips,” IEEE Journal of Solid-State Circuits, vol. SC-7, pp. 389–395, 1972.CrossRefGoogle Scholar
- [48]A. Gupta, W. A. Porter, and J. A. Lathrop, “Defect Analysis and Yield Degradation of Integrated Circuits,” IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 96–102, 1974.CrossRefGoogle Scholar
- [49]H. Murrmann and D. Kranzer, “Yield Modeling of Integrated Circuits,” Siemens Forschungs und Entwicklung Berichte, vol. 9, pp. 38–40, February, 1980.Google Scholar
- [50]J. C. Harden and N. R. Strader II, “Architectural Yield Optimization for WSI,” IEEE Transactions on Computers, vol. C-37, pp. 88–110, 1988.CrossRefGoogle Scholar
- [51]G. A. Magó, “A Network of Microprocessors to Execute Reduction Languages,” Two Parts. International Journal of Computer and Information Sciences, vol. 8, pp. 349–385 and pp. 435–471, 1979.MathSciNetMATHCrossRefGoogle Scholar
- [52]G. A. Magó, “A Cellular Computer Architecture for Functional Programming,” Proceedings of COMPCON, pp. 179–187, Spring, 1980.Google Scholar
- [53]J. Backus, “Can Programming Be Liberated from the von Neumann Style? A Functional Style and Its Algebra of Programs,” Communications of the Association for Computing Machinery, vol. 8, pp. 613–641, 1978.MathSciNetCrossRefGoogle Scholar
- [54]C. Mead and L. Conway, Introduction to VLSI Systems, Reading, MA: Addison-Wesley, 1980.Google Scholar
- [55]G. A. Magó and D. Middleton, “The FFP Machine — A Progress Report,” Proceedings of the International Workshop on High-Level Computer Architecture, Los Angeles, CA, May, 1984.Google Scholar
- [56]C. S. Raghavendra, A. Avizienis, and M. Ercegovac, “Fault-Tolerance in Binary Tree Architectures,” Proceedings of the 13th International Symposium on Fault-Tolerant Computing, pp. 360–364, 1983.Google Scholar
- [57]D. Gordan, I. Koran, and G. M. Silberman, “Embedding Tree Structures in VLSI Hexagonal Arrays,” IEEE Transactions on Computers, vol. C-33, pp. 104–108, 1984.CrossRefGoogle Scholar
- [58]J. C. Harden, “A Wafer Scale Cellular Tree Architecture,” Ph.D. dissertation, Texas A&M University, June, 1985.Google Scholar

## Copyright information

© Kluwer Academic Publishers 1989