Introduction

Abstract

Programmable systolic arrays are attractive for high speed scientific computing because of their truly scalable architecture. However, systolic array programming has been an intellectually challenging problem since the architecture was made popular by H. T. Kung in the late 1970s. For many years, researchers have been studying compiler techniques for mapping scientific programs to systolic arrays [5, 7, 12, 14]. However, these efforts were focused on hard-wired systolic arrays, and thus many of their results are not directly applicable in the context of programmable systolic arrays. In a hard-wired systolic array, the functions of the processing cells, the size of the array, and the intercell connections are selected to perform a dedicated computation on a fixed problem size. Whereas in a programmable systolic array, the size of the array and the intercell connections are fixed, and the processing cells can be programmed to perform different computations on different problem sizes.