Transmission-Gate Logic

Abstract

Our experience with NMOS logic circuits using transmission gates as switches suggests that we may extend the technique to GaAs circuits. However, the lack of DC isolation between the gate and the source or drain in a GaAs MESFET makes the use of the transmission gate problematic. Fig. 4.1 shows a transmission gate which is either a depletion or enhancement transistor. The circuit is symmetrical with respect to the gate, and current can flow from node 1 to node 2, or vice versa, depending on whether V₁ is greater or less than V₂. Without loss of generality, node 1 will be taken as the input and node 2 the output, which is usually connected to an inverter whose loading effect is approximated by the capacitance C. If the control signal, usually the gate voltage, is sufficiently positive with respect to either the drain or source voltage, gate current will flow and the control signal will appear at the output. In addition, if the gate-to-source or gate-to-drain capacitance is comparable to the load capacitance C, a significant fraction of the control signal will be at the output and a logical error may be produced at the output of the inverter. Nevertheless, if the amplitude of the control voltage is limited to certain range of values, the feed-through can be minimized and the transmission gate can be used as a voltage-controlled switch.