Design for Testability

Abstract

This chapter investigates some design methods aimed at making logic circuits more amenable to testing using the test generation technique proposed in Chapter 3. It is clear from the previous two chapters that this approach is particularly well suited to circuits such as ripple-carry adders and parity checkers which contain repeated subcircuits interconnected in a regular fashion. A bus-oriented high-level model can be easily constructed following the procedure PSC of Fig. 2.17, so that a test set for an total bus faults in the resulting model detects all, or nearly all, SSL faults in the circuit. The scope of our testing methodology can be broadened considerably by formulating some design-for-testability techniques for circuits like carry-lookahead generators, counters, and decoders, etc., which take the form of slightly irregular array or tree circuits. The presence of irregularity makes the construction of high-level models for the unmodified circuits difficult, and complicates test generation. In this chapter, we consider redesigning circuits of this sort to enhance their regularity, and make them better suited to test generation using hierarchical approaches.