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Test Generation for Static CMOS Circuits

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Testing and Reliable Design of CMOS Circuits

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 88))

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Abstract

In the previous chapter we discussed testing methods for combinational dynamic CMOS circuits. In this chapter we will concentrate on combinational static CMOS circuits. Test generation for a static CMOS circuit, as in the case of a dynamic CMOS circuit, can be done from either its gate-level model or its transistor-level description. We will discuss both the approaches.

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Authors and Affiliations

  1. Princeton University, USA

    Niraj K. Jha

  2. T.J. Watson Research Center, IBM, USA

    Sandip Kundu

Authors
  1. Niraj K. Jha
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  2. Sandip Kundu
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© 1990 Kluwer Academic Publishers

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Jha, N.K., Kundu, S. (1990). Test Generation for Static CMOS Circuits. In: Testing and Reliable Design of CMOS Circuits. The Kluwer International Series in Engineering and Computer Science, vol 88. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1525-4_4

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  • DOI: https://doi.org/10.1007/978-1-4613-1525-4_4

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8818-3

  • Online ISBN: 978-1-4613-1525-4

  • eBook Packages: Springer Book Archive

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