Abstract
CMOS has become a very popular technology because of its low-power requirement and high density. However, an increase in the density of the chips also increases the complexity of testing. To further add to the woes of a testing engineer, new mechanisms have been identified through which a test derived for a CMOS circuit may be invalidated. In other words, a test may not be able to do its intended job. This is the topic of discussion in this chapter.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
L. G. Heller et al., “Cascode voltage switch logic: A differential CMOS logic family,” in Proc. Int. Solid-State Circuits Conf., pp. 16–17, Feb. 1984.
S. K. Jain and V. D. Agrawal, “Test generation for MOS circuits using D-algorithm,” in Proc. Design Automation.Conf, Miami Beach, FL, pp. 64–70, June 1983.
R. H. Krambeck, C. M. Lee, and H.-F. S. Law, “Highspeed compact circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614–619, June 1982.
S. M. Reddy, M. K. Reddy, and J. G. Kuhl, “On testable design for CMOS logic circuits,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 435–445, Oct. 1983.
S. M. Reddy and M. K. Reddy, “Testable realizations for FET stuck-open faults in CMOS combinational logic circuits,” IEEE Trans. Comput., vol. C-35, pp. 742–754, Aug. 1986.
N. Weste and K. Eshraghian, Principles of CMOS VLSI design: A systems perspective, Addison-Wesley, Reading, Mass., 1985.
Additional Reading
P. Agrawal, “Test generation at the switch level,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 128–130, Nov. 1984.
G. Gupta and N. K. Jha, “A universal test set for CMOS circuits,” IEEE Trans. CAD, vol. 7, pp. 590–597, May 1988.
N. K. Jha and J. A. Abraham, “Design of testable CMOS circuits under arbitrary delays,” IEEE Trans. CAD, vol. CAD-4, pp. 264–269, July 1985.
S. Kundu and S. M. Reddy, “On the design of robust testable combinational logic circuits,” in Proc. Int. Symp. Fault-Tolerant Comput., Tokyo, Japan, pp. 220–225, June 1988.
S. Kundu, S. M. Reddy, and N. K. Jha, “On the design of robust multiple fault testable CMOS combinational logic circuits,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 240–243, Nov. 1988.
P. S. Moritz and L. M. Thorsen, “CMOS circuit testability,” IEEE J. Solid-State Circuits, vol. SC-21, no. 2, pp. 306–309, Apr. 1986.
S. M. Reddy, M. K. Reddy, and V. D. Agrawal, “Robust tests for stuck-open faults in CMOS combinational circuits,” in Proc. Int. Symp. Fault-Tolerant Comput., Orlando, FL, pp. 44–49, June 1984.
S. D. Sherlekar and P. S. Subramanian, “Conditionally robust two-pattern tests and CMOS design for testability,” IEEE Trans. CAD, vol. 7, pp. 325–332, Mar. 1988.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1990 Kluwer Academic Publishers
About this chapter
Cite this chapter
Jha, N.K., Kundu, S. (1990). Test Invalidation. In: Testing and Reliable Design of CMOS Circuits. The Kluwer International Series in Engineering and Computer Science, vol 88. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1525-4_2
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1525-4_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8818-3
Online ISBN: 978-1-4613-1525-4
eBook Packages: Springer Book Archive