Skip to main content
SpringerLink
Log in

Introduction

  • Chapter
Testing and Reliable Design of CMOS Circuits

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 88))

  • 116 Accesses

Abstract

Very Large Scale Integration (VLSI) has enabled us to implement very complex circuits on a single chip. Complementary Metal Oxide Semiconductor (CMOS) technology has played a dominant role in allowing this to happen. The advantages of VLSI circuits are obvious. However, they do pose a problem. The problem is how do we test the VLSI chips to ensure that they function as they are supposed to. With chips containing a million or more transistors, testing has become a difficult and time-consuming job. Testing is becoming an increasing part of the time it takes from conception to marketing of a chip. This problem can only become more severe in the future.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J. A. Abraham and W. K. Fuchs, “Fault and error models for VLSI,” Proc. IEEE, vol. 74, no. 5, pp. 639–654, May 1986.

    Article  Google Scholar 

  2. M. Abramovici and P. R. Menon, “A practical approach to fault simulation and test generation for bridging faults,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 138–142, Oct. 1983.

    Google Scholar 

  3. J. M. Acken, “Testing for bridging faults (shorts) in CMOS circuits,” in Proc. Design Automation Conf., Miami Beach, FL, pp. 717–718, June 1983.

    Google Scholar 

  4. D. Baschiera and B. Courtois, “Advances in fault modeling and test pattern generation for CMOS,” in Proc. Int. Conf. Computer Design, Port Chester, NY, pp. 82–85, Oct. 1986.

    Google Scholar 

  5. R. K. Brayton and C. McMullen, “The decomposition and factorization of Boolean expressions,” in Proc. Int. Symp. Circuits & Systems, Rome, Italy, pp. 49–54, June 1982.

    Google Scholar 

  6. G. R. Case, “Analysis of actual fault mechanisms in CMOS logic gates,” in Proc. Design Automation Conf., San Francisco, CA, pp. 265–270, June 1976.

    Google Scholar 

  7. X. Castillo, S. R. McConnel, and D. P. Siewiorek, “Derivation and calibration of a transient error reliability model,” IEEE Trans. Comput., vol. C-31, pp. 658–671, July 1982.

    Article  Google Scholar 

  8. K. M. Chu and D. L. Pulfrey, “Design procedures for differential cascode voltage switch circuits,” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 1082–1087, Dec. 1986.

    Article  Google Scholar 

  9. K. M. Chu and D. L. Pulfrey, “A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic,” IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 528–532, Aug. 1987.

    Article  Google Scholar 

  10. Y. M. El-Ziq and R. J. Cloutier, “Functional-level test generation for stuck-open faults in CMOS VLSI,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 536–546, Oct. 1981.

    Google Scholar 

  11. F. J. Ferguson and J. P. Shen, “A CMOS fault extractor for inductive fault analysis,” IEEE Trans. CAD, vol. 7, pp. 1181–1194, Nov. 1988.

    Google Scholar 

  12. A. D. Friedman, “Diagnosis of short-circuit faults in combinational circuits,” IEEE Trans. Comput., vol. C-23, pp. 746–752, July 1974.

    Article  Google Scholar 

  13. V. Friedman and S. Liu, “Dynamic logic CMOS circuits,” IEEE J. Solid-State Circuits, vol. SC-19, no. 2, pp. 263–266, Apr. 1984.

    Article  Google Scholar 

  14. N. F. Goncalves and H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits, vol. SC-18, no. 3, pp. 261–266, June 1983.

    Article  Google Scholar 

  15. T. A. Grotjohn and B. Hoefflinger, “Sample-set differential logic (SSDL) for complex Highspeed VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, no. 2, pp. 367–369, Apr. 1986.

    Article  Google Scholar 

  16. J.P. Hayes, “Fault modeling,” IEEE Design & Test, vol. 2, no. 2, pp. 88–95, Apr. 1985.

    Article  MathSciNet  Google Scholar 

  17. L. G. Heller et al., “Cascode voltage switch logic: A differential CMOS logic family,” in Proc. Int. Solid-State Circuits Conf., pp. 16–17, Feb. 1984.

    Google Scholar 

  18. I. S. Hwang and A. L. Fisher, “Ultrafast compact 32-bit CMOS adders in multiple-output domino logic,” IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 358–369, Apr. 1989.

    Article  Google Scholar 

  19. A. Iosupovicz, “Optimal detection of bridging faults and stuck-at faults in two-level logic,” IEEE Trans. Comput., vol. C-27, no. 5, pp. 452–455, May 1978.

    Article  MathSciNet  Google Scholar 

  20. R. K. Iyer and D. J. Rossetti, “Permanent CPU errors and systems activity: Measurement and modeling,” in Proc. Real-Time Syst. Symp., Arlington, VA, pp. 61–72, Dec. 1983.

    Google Scholar 

  21. N. K. Jha and J. A. Abraham, “Design of testable CMOS circuits under arbitrary delays,” IEEE Trans. CAD, vol. CAD-4, pp. 264–269, July 1985.

    Google Scholar 

  22. Y. Ji-Ren, I. Karlsson, and C. Svensson, “A true single-phase-clock dynamic CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pp. 899–901, Oct. 1987.

    Article  Google Scholar 

  23. I. Karlsson, “True single phase clock dynamic CMOS circuit technique,” in Proc. Int. Symp. Circuits & Systems, Espoo, Finland, pp. 475–478, June 1988.

    Google Scholar 

  24. M. Karpovsky, “Universal tests for detection of input/output stuck-at and bridging faults,” IEEE Trans. Comput., vol. C-32, no. 12, pp. 1194–1198, Dec. 1983.

    Article  MathSciNet  Google Scholar 

  25. K. L. Kodandapani and D. K. Pradhan, “Undetectability of bridging faults and validity of stuck-at fault test sets,” IEEE Trans. Comput., vol. C-29, no. 1, pp. 55–59, Jan. 1980.

    Article  MathSciNet  Google Scholar 

  26. R. H. Krambeck, C. M. Lee, and H.-F. S. Law, “Highspeed compact circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614–619, June 1982.

    Article  Google Scholar 

  27. C. M. Lee and E. W. Szeto, “Zipper CMOS,” IEEE Circuits & Devices, pp. 10-17, May 1986.

    Google Scholar 

  28. M. W. Levi, “CMOS is most testable,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 217–220, Oct. 1981.

    Google Scholar 

  29. S.-H. Lu, “Implementation of iterative networks with CMOS differential logic,” IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 1013–1017, Aug. 1988.

    Article  Google Scholar 

  30. Y. K. Malaiya and S. Y. H. Su, “A new fault model and testing technique for CMOS devices,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 25–34, Oct. 1982.

    Google Scholar 

  31. Y. K. Malaiya, “Testing stuck-on faults in CMOS integrated circuits,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 248–250, Nov. 1984.

    Google Scholar 

  32. Y. K. Malaiya, A. P. Jayasumana, and R. Rajsuman, “A detailed examination of bridging faults,” in Proc. Int. Conf. Computer Design, Port Chester, NY, pp. 78–81, Oct. 1986.

    Google Scholar 

  33. W. Maly, P. K. Nag, and P. Nigh, “Testing oriented analysis of CMOS ICs with opens,” in Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, pp. 344–347, Nov. 1988.

    Google Scholar 

  34. K. C. Y. Mei, “Bridging and stuck-at faults,” IEEE Trans. Comput., vol. C-23, no. 7, pp. 720–727, July 1974.

    Article  Google Scholar 

  35. L. C. Pfennings et al., “Differential split-level CMOS logic for subnanosecond speeds,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1050–1055, Oct. 1985.

    Article  Google Scholar 

  36. J. A. Pretorius, A. S. Shubat, and C. A. T. Salama, “Latched domino CMOS logic,” IEEE J. Solid-State Circuits, vol. SC-21, no. 4, pp. 514–522, Aug. 1986.

    Article  Google Scholar 

  37. S. M. Reddy, V. D. Agrawal, and S. K. Jain, “A gate-level model for CMOS combinational logic circuits with application to fault detection,” in Proc. Design Automation Conf., Albuquerque, NM, pp. 504–509, June 1984.

    Google Scholar 

  38. S. M. Reddy and M. K. Reddy, “Testable realizations for FET stuck-open faults in CMOS combinational logic circuits,” IEEE Trans. Comput., vol. C-35, pp. 742–754, Aug. 1986.

    Article  Google Scholar 

  39. J. P. Shen, W. Maly, and F. J. Ferguson, “Inductive fault analysis of MOS integrated circuits,” IEEE Design & Test, vol. 2, no. 6, pp. 13–26, Dec. 1985.

    Article  Google Scholar 

  40. O. Tasar and V. Tasar, “A study of intermittent faults in digital computers,” in Proc. AFIPS Conf., pp. 807–811, 1977.

    Google Scholar 

  41. C. Timoc et al., “Logical models of physical failures,” in Proc. Int. Test Conf., Philadelphia, PA, pp. 546–553, Oct. 1983.

    Google Scholar 

  42. S. Tsukiyama, H. Ariyoshi, and I. Shirakawa, “Algorithm to enumerate all the cutsets in O(∣V∣+∣E∣) time per cutset,” in Proc. Int. Symp. Circuits & Systems, Tokyo, Japan, pp. 645–648, June 1979.

    Google Scholar 

  43. R. L. Wadsack, “Fault modeling and logic simulation of CMOS and MOS integrated circuits,” Bell Syst. Tech. J., vol. 57, no. 5, pp. 1449–1474, May-June 1978.

    MATH  Google Scholar 

  44. N. Weste and K. Eshraghian, Principles of CMOS VLSI design: A systems perspective, Addison-Wesley, Reading, Mass., 1985.

    Google Scholar 

  45. S. Xu and S. Y. H. Su, “Testing feedback bridging faults among internal, input and output lines by two patterns,” in Proc. Int. Conf. Circuits & Computers, New York, NY, pp. 214–217, Oct. 1982.

    Google Scholar 

  46. T. Yamada and T. Nanya, “Stuck-at fault tests in the presence of undetectable bridging faults,” IEEE Trans. Comput., vol. C-33, no. 8, pp. 758–761, Aug. 1984.

    Article  Google Scholar 

  47. M. Y. Yen, W. K. Fuchs, and J. A. Abraham, “Designing for concurrent error detection in VLSI: Application to a microprogram control unit,” IEEE J. Solid-State Circuits, vol. SC-22, no. 4, pp. 595–605, Aug. 1987.

    Article  Google Scholar 

  48. J. Yuan and C. Svensson, “Highspeed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62–70, Feb. 1989.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Princeton University, USA

    Niraj K. Jha

  2. T.J. Watson Research Center, IBM, USA

    Sandip Kundu

Authors
  1. Niraj K. Jha
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sandip Kundu
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

Copyright information

© 1990 Kluwer Academic Publishers

About this chapter

Cite this chapter

Jha, N.K., Kundu, S. (1990). Introduction. In: Testing and Reliable Design of CMOS Circuits. The Kluwer International Series in Engineering and Computer Science, vol 88. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1525-4_1

Download citation

  • DOI: https://doi.org/10.1007/978-1-4613-1525-4_1

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8818-3

  • Online ISBN: 978-1-4613-1525-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation