This chapter describes several examples of the statistical analysis of IC performance. The first section is devoted to the description of the new approach to statistical timing analysis which offers a very significant improvement in the speed of evaluating the timing behavior of digital MOS IC’s. This approach is especially well suited for the statistical design purposes such as design centering or worst-case design. The latter is the subject of the next section in which the worst-case analysis is formalized. A software system, WORCAN, is also described in this section together with some computational examples. Finally, the last section describes an approach to statistical optimization of the functional blocks of IC’s. The optimization is carried out in terms of both layout and process control parameters. FABRICS is used in all the examples in this chapter to generate the data for statistical analysis.
KeywordsPower Dissipation Transition Time Circuit Simulation Device Parameter Input Delay
Unable to display preview. Download preview PDF.
- 1.This section is based on the paper ▪A New Approach to Hierarchical and Statistical Timing Simulations▪ by J. Benkoski and A. J. Strojwas, IEEE Trans. on CAD of ICAS, vol. 6, pp. 1039-1052, 1987Google Scholar
- 2.This section is based upon the paper ▪A Methodology for Worst-Case Analysis of Integrated Circuits▪ by S.R. Nassif, A.J. Strojwas and S.W. Director, IEEE Trans. on CARD of ICAS, vol. 5, pp. 104-113, 1986Google Scholar
- 4.This section is based upon the paper ▪Optimal Design of VLSI Minicells Using a Statistical Process Simulator▪ by A.J. Strojwas, S.R. Nassif and S.W. Director, In Proc. of 1983 ISCAS, May, 1983Google Scholar