Skip to main content
SpringerLink
Log in

Multidimensional Systolic Arrays for Computing Discrete Fourier Transforms and Discrete Cosine Transforms

  • Chapter
Application Specific Processors

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 380))

Abstract

This chapter presents a new approach for computing the multidimensional discrete Fourier transform (DFT) and the multidimensional discrete cosine transform (DCT) in a multidimensional systolic array. There are extensive applications of fast Fourier transform (FFT) and fast cosine transform (FDCT) algorithms. From the basic principle of fast transform algorithms (breaking the computation in successively smaller computations), we find that the multidimensional systolic architecture is efficiently used for implementing FFT algorithms and FDCT algorithms. The essence of the multidimensional systolic array is to combine different types of semi-systolic arrays into one array so that the resulting array becomes truly systolic. This systolic array does not require any preloading of input data and it generates output data only from boundary PEs. No networks for transposition between intermediate constituent 1-D transforms are required; therefore the entire processing is fully pipelined. This approach is well suited for VLSI implementation by providing simple and regular structures. Complexity estimation of area*time 2 shows our multidimensional systolic array is within a factor of logk of the lower bound for an M-dimensional k-point DFT (k=N M).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing, Englewood Cliffs, NJ: Prentice-Hall, 1989.

    MATH  Google Scholar 

  2. I. Gertner and M. Shamash, “VLSI Architectures for Multidimensional Fourier Transform Processing,” IEEE Trans. on Computers, Vol. C-36, 1987, pp. 1265–1274.

    Article  Google Scholar 

  3. S. Y. Kung, VLSI Array Processors, Englewood Cliffs, NJ: Prentice-Hall, 1988.

    Google Scholar 

  4. H. T. Kung, “Memory Requirements for Balanced Computer Architecture,” Proc. 13th Annual Int. Symp. on Computer Architecture, June 1986, pp. 49–54.

    Google Scholar 

  5. N. R. Murthy and M. N. S. Swamy, “On die Real-Time Computation of DFT and DCT through Systolic Architectures”, IEEE Trans, on Signal Processing, Vol. 42, Apr. 1994, pp. 988–991.

    Article  Google Scholar 

  6. E. E. Swartzlander, “Systolic FFT Processors,” W. Moore, A. McCabe, and R. Urquhart, eds., Proceedings International Workshop on Systolic Arrays, Boston: Adam Hilger, 1987, pp. 133–140.

    Google Scholar 

  7. E. E. Swartzlander, ed., Systolic Signal Processing Systems, New York: Marcel Dekker, Inc., 1987.

    Google Scholar 

  8. T. D. Roziner and M.G. Karpovsky, “Multidimensional Fourier Transforms by Systolic Architectures,” Journal of VLSI Signal Processing, 4, 1992, pp. 343–354.

    Article  Google Scholar 

  9. M. H. Lee, “High Speed Multidimensional Systolic Arrays for Discrete Fourier Transform,” IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 39, 1992, pp. 876–879.

    Article  MATH  Google Scholar 

  10. H. S. Lim, “A Study on die Parallel Processing Architectures for 2-D Discrete Cosine Transform,” M. S. Thesis, Ch. 3, Seoul National University, Korea, 1991.

    Google Scholar 

  11. H. S. Lim and Earl E. Swartzlander, Jr., “A Systolic Array for 2-D DFT and 2-D DCT,” International Conference on Application-Specific Array Processors, Aug. 1994, pp. 123–131.

    Google Scholar 

  12. H. S. Lim and Earl E. Swartzlander, Jr., “An Efficient Systolic Array for DCT Based on Prime-Factor Decomposition,” International Conference on Computer Design, Oct. 1995, pp. 644–649.

    Google Scholar 

  13. H. S. Lim and Earl E. Swartzlander, Jr., “Efficient Systolic Arrays for FFT Algorithms,” 29th Annual Asilomar Conference on Signals, Systems, and Computers, Oct. 1995, pp.141–145.

    Google Scholar 

  14. H. S. Lim and Earl E. Swartzlander, Jr., “Multidimensional Systolic Arrays for Multidimensional DFTs,” IEEE International Conference on Acoustics, Speech & Signal Processing, May 1996, pp. 3277–3280.

    Google Scholar 

  15. H. S. Lim, C. Yim and Earl E. Swartzlander, Jr., “Finite Word-Length Effects of a 2-D DCT Systolic Array,” International Conference on Application-Specific Array Processors, Aug. 1996.

    Google Scholar 

  16. N. Ling and M.A. Bayoumi, “An Algoridim Transformation Technique for Multi-Dimensional DSP Systolic Arrays,” IEEE International Symposium on Circuits and Systems, 1988, pp. 2275–2278.

    Google Scholar 

  17. C. N. Zhang and D.Y.Y. Yun, “Multi-Dimensional Systolic Networks for Discrete Fourier Transform,” Proc. 11 th Int. Symp. Computer Architecture, Ann Arbor, Mich., 1984, pp. 215–222.

    Google Scholar 

  18. G. H. Allen, P.B. Denyer, and D. Renshaw, “A Bit Serial Linear Array DFT,” IEEE International Conference on Acoustics, Speech & Signal Processing, San Diego, 1988, pp. 41A.1.1–41A.1.4.

    Google Scholar 

  19. M.A. Bayoumi, G.A. Jullien, and W.C. Miller, “A VLSI Array for Computing the DFT based on RNS,” IEEE International Conference on Acoustics, Speech & Signal Processing, Tokyo, 1986, pp. 2147–2150.

    Google Scholar 

  20. J. A. Beraldin, T. Aboulnasr, and W. Steenaart, “Efficient One-Dimensional Systolic Array Realization of die Discrete Fourier Transform,” IEEE Trans. Circuits and Systems, Vol. 36, 1989, pp. 95–100.

    Article  Google Scholar 

  21. L.W. Chang and M.Y. Chen, “A New Systolic Array for Discrete Fourier Transform,” IEEE Trans. Acoustics, Speech, and Signal Processing, Vol. ASSP-36, 1988, pp. 1665–1666.

    Article  Google Scholar 

  22. J. Guo, C. Liu, and C. Jen, “The Efficient Memory-based VLSI Array Designs for DFT and DCT,” IEEE Trans, on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 39, 1992, pp. 723–733.

    Article  MATH  Google Scholar 

  23. D. C. Kar and V.V. Rao, “A New Systolic Realization for Discrete Fourier Transform,” IEEE Trans, on Signal Processing, Vol. 41, 1993, pp. 2008–2010.

    Article  MATH  Google Scholar 

  24. B. G. Lee, “A New Algorithm to Compute die Discrete Cosine Transform,” IEEE Trans. Acoustics, Speech, and Signal Processing, Vol. ASSP-32, 1984, pp. 1243–1245.

    Google Scholar 

  25. C. Chakrabarti and J. Ja’Ja’, “Systolic Architectures for the Computation of the Discrete Hartley and die Discrete Cosine Transforms Based on Prime Factor Decomposition,” IEEE Trans, on Computers, Vol. 39, Nov. 1990, pp. 1359–1368.

    Article  MathSciNet  Google Scholar 

  26. B. G. Lee, “Input and Output Index Mappings for a Prime-Factor-Decomposed Computation of Discrete Cosine Transform,” IEEE Trans, on Acoust., Speech, and Signal Processing, Vol. 37, Feb. 1989, pp. 237–244.

    Article  MATH  Google Scholar 

  27. J. Canaris, “A VLSI Architecture for die Real Time Computation of Discrete Trigonometric Transforms,” Journal of VLSI Signal Processing, Vol. 5, 1993, pp. 95–104.

    Article  MATH  Google Scholar 

  28. M. Sheu, J. Lee, J. Wang, A. Suen, and L. Liu, “A High Throughput-rate Architecture for 8*8 2-D DCT,” IEEE International Symposium on Circuits and Systems, Vol. 3, 1993, pp. 1587–1590.

    Google Scholar 

  29. N. I. Cho and S. U. Lee, “DCT Algorithms for VLSI Parallel Implementation,” IEEE Trans. Acoustics, Speech, and Signal Processing, Vol. ASSP-38, 1990, pp. 121–127.

    Google Scholar 

  30. C. D. Thompson, “Fourier Transforms in VLSI,” IEEE Trans, on Computers, Vol. C-32, 1983, pp. 1047–1057.

    Article  Google Scholar 

  31. A. D. Boodi, “A Signed Binary Multiplication Technique,” Quarterly Journal of Mechanics and Applied Mathematics, Vol. 4, 1951, pp. 236–240.

    Article  MathSciNet  Google Scholar 

  32. S. Magar, S. Shen, G. Luikuo, M. Fleming, and R. Agular, “An Application Specific Chipset for 100 MHz data rate,” IEEE International Conference on Acoustics, Speech & Signal Processing, 1988, pp.1989–1992.

    Google Scholar 

  33. J. O’Brien, J. Mather, and B. Holland, “A 200 MIPS Single-Chip IK FFT Processor,” Proc. 1989 IEEE Int. Solid-State Circuits Conf, 1989, pp. 166–167.

    Google Scholar 

  34. R. M. Owens and J. Ja’Ja, “A VLSI Chip for the Winograd/Prime Factor Algorithm to Compute die Discrete Fourier Transform,” IEEE Trans, on Acoust., Speech, and Signal Processing, Vol. 34, 1986, pp. 979–989.

    Article  Google Scholar 

  35. T. K. Truong, I. S. Reed, I. S. Hsu, H. C. Shyu, and H. M. Shao, “A Pipeline Design of a Fast Prime Factor DFT on a Finite Field,” IEEE Trans, on Computers, Vol. 37, 1988, pp. 266–273.

    Article  MathSciNet  MATH  Google Scholar 

  36. C. S. Burrus, “Index Mappings for Multidimensional Formulation of the DFT and Convolution,” IEEE Trans. AcoustSpeech, and Signal Processings, Vol. 25, 1977, pp. 239–242.

    Article  MATH  Google Scholar 

  37. I. Niven and H. S. Zuckennan, An Introduction to the Theory of Numbers, John Wiley & Sons, Third Edition, Ch. 2, 1972.

    MATH  Google Scholar 

  38. P. Z. Lee and F. Y. Huang, “An Efficient Prime-Factor Algoridims for the Discrete Cosine Transform and and Its Hardware Implementations,” IEEE Trans, on Signal Processing, Vol. 42, Aug. 1994, pp. 1996–2005.

    Article  Google Scholar 

  39. P. P. N. Yang and M. J. Narasimha, “Prime Factor Decomposition of the Discrete Cosine Transform and Its Hardware Realization,” IEEE International Conference on Acoustics, Speech & Signal Processing, 1985, pp. 20.5.1–20.5.4.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, Austin, USA, TX

    Hyesook Lim

Authors
  1. Hyesook Lim
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. University of Texas at Austin, USA

    Earl E. Swartzlander Jr.

Rights and permissions

Reprints and permissions

Copyright information

© 1997 Kluwer Academic Publishers

About this chapter

Cite this chapter

Lim, H. (1997). Multidimensional Systolic Arrays for Computing Discrete Fourier Transforms and Discrete Cosine Transforms. In: Swartzlander, E.E. (eds) Application Specific Processors. The Kluwer International Series in Engineering and Computer Science, vol 380. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1457-8_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4613-1457-8_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8635-6

  • Online ISBN: 978-1-4613-1457-8

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation