Abstract
CMOS digital multipliers have high power dissipation in comparison with other circuits due to carry propagation and spurious transitions. Techniques to reduce switching activity and improve the performance at the algorithm and circuit level are presented. A new concept to reduce switching activity using combinational self-timed elements and bypassing logic blocks to eliminate redundant operations is proposed.
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© 1997 Kluwer Academic Publishers
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de Angel, E. (1997). Low Power Digital Multipliers. In: Swartzlander, E.E. (eds) Application Specific Processors. The Kluwer International Series in Engineering and Computer Science, vol 380. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1457-8_4
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DOI: https://doi.org/10.1007/978-1-4613-1457-8_4
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