Abstract
This chapter summarizes various techniques used to achieve fault tolerance in computer arithmetic. There are basically three approaches including hardware redundancy, information redundancy, and time redundancy. Hardware redundancy has the highest hardware overhead. However, its delay is minimal. In the information redundancy approach, both the hardware complexity and delay are higher than other approaches. Time redundancy uses the smallest amount of hardware at the expense of extra computation time. In this research a concurrent error correcting technique based on time redundancy called time shared TMR is developed. It has been successfully applied to ripple carry adders and array multipliers. VLSI ripple carry adders and array multipliers are designed. They are compared in area, delay and cycle time. The time shared TMR technique can also be applied to more complex arithmetic processors like sorting networks, FFT arrays, convolvers, and inner product units. This research is significant because the time shared TMR technique proves to be a high reliability, low hardware complexity, and reasonable delay penalty solution to fault tolerant arithmetic.
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References
B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Reading, MA: Addison-Wesley, 1989.
J. L. A. Hughes, E. J. McCluskey, and D. J. Lin, “Design of totally selfchecking comparators with an arbitrary number of inputs,” Proc. 1983 Int’l Symp. Fault-Tolerant Comput., pp. 169–172.
G. York, D. P. Siewiorek, and Y. X. Zhu, “Compensating faults in triple-modular redundancy,” Proc. 1985 Int’l Symp. Fault-Tolerant Comput., pp. 226–231.
B. W. Johnson, “Fault-tolerant microprocessor-based systems,” IEEE Micro, Vol. 4, No. 6, pp. 6–21, 1984.
P. R. Lorczak, A. K. Caglayan, and D. E. Eckhardt, “A theoretical investigation of generalized voters for redundant systems,” Proc. 1989 Int’l Symp. Fault-Tolerant Comput., pp. 444–451.
X. Zhuo and S. Li, “A new design method of voter in fault-tolerant redundancy multiple-module multi-microcomputer system,” Proc. 1983 Int’l Symp. Fault-Tolerant Comput., pp. 472–475.
T. R. Rao, Error Coding for Arithmetic Processors, New York, NY: Academic Press, 1974.
T. R. N. Rao and E. Fujiwara, Error-Control Coding for Computer Systems, Englewood Cliffs, NJ: Prentice-Hall, 1989.
J. M. Berger, “A note on error detecting codes for asymmetric channels,” Info. & Control, Vol. 4, pp. 68–73, March 1961.
J.-C. Lo, S. Thanawastien, and T. R. N. Rao, “Concurrent error detection in arithmetic and logical operations using Berger codes,” Proc. 1989 Symp. Computer Arith., pp. 233–240.
J. H. Kim, et al, “The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays,” Proc. 1993 Int’l Conf Wafer Scale Integ., pp. 163–172.
N. Takagi and S. Yajima, “An on-line error-detectable array divider with a redundant binary representation and a residue code,” Proc. 1988 Int’l Symp. Fault-Tolerant Comput., pp. 174–179.
J.-C. Lo, S. Thanawastien, and T. R. N. Rao, “Berger check prediction for array multipliers and array dividers,” IEEE Trans. Comput., Vol. 42, pp. 892–896, 1993.
J.-C. Lo, “Reliable floating-point arithmetic algorithms for error coded operands,” IEEE Trans. Comput., Vol. 43, pp. 400–412, 1994.
D. Reynolds and G. Metze, “Fault detection capabilities of alternating logic,” IEEE Trans. Comput., Vol. C-27, pp. 1093–1098, 1978.
Z. Kohavi, Switching and Finite Automata Theory, New York, NY: McGraw-Hill, 1978.
K. Takeda and Y. Tohma, “Logic design of fault-tolerant arithmetic units based on the data complementation strategy,” Proc. 1980 Int’l Symp. Fault-Tolerant Comput., pp. 348–350.
K. Furuya, Y. Akita, and Y. Tohma, “Logic design of fault-tolerant dividers based on data complementation strategy,” Proc. 1983 Int’l Symp. Fault-Tolerant Comput., pp. 306–313.
J. Patel and L. Fung, “Concurrent error detection in ALU’s by recomputing with shifted operands,” IEEE Trans. Comput., Vol. C-31, pp. 589–595, 1982.
W.-T. Cheng and J. H. Patel, “Concurrent error detection in iterative logic arrays,” Proc. 1984 Int’l Symp. Fault-Tolerant Compute., pp. 10–15.
B. W. Johnson, J. H. Aylor, and H. H. Hana, “Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder,” IEEE J. Solid-State Circuits, Vol. 23, pp. 208–215, 1988.
G. S. Sohi, M. Franklin, and K. K. Saluja, “A study of time-redundant fault tolerance techniques for high-performance pipelined computers,” Proc. 1989 Int’l Symp. Fault-Tolerant Compute., pp. 436–443.
J. H. Patel and L. Y. Fung, “Multiplier and divider arrays with concurrent error detection,” Proc. 1982 Int’l Symp. Fault-Tolerant Compute., pp. 325–329.
J. H. Patel and L. Y. Fung, “Concurrent error detection in multiply and divide arrays,” IEEE Trans. Compute., Vol. C-32, pp. 417–422, 1983.
S. Lala and J. H. Patel, “Error correction in arithmetic operations using time redundancy,” Proc. 1983 Int’l Symp. Fault-Tolerant Compute., pp. 298–305.
J. Li and E. E. Swartzlander, Jr., “Concurrent error detection in ALUs by recomputing with rotated operands,” Proc. 1992 IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 109–116.
L. G. Chen and T. H. Chen, “Fault-tolerant serial-parallel multiplier,” IEE Proc.-E, Vol. 138, pp. 276–280, 1991.
L. G. Chen and T. H. Chen, “Computation with simultaneously concurrent error detection using bi-directional operands,” Proc. 1989 Int’l Conf. Comput. Design, pp. 128–131.
L. H. Pollard and J. H. Patel, “Correction of errors in data transmission using time redundancy,” Proc. 1983 Int’l Symp. Fault-Tolerant Comput., pp. 314–317.
A. Majumdar, C. S. Raghavendra, and M. A. Breuer, “Fault tolerance in linear systolic arrays using time redundancy,” IEEE Trans. Comput., Vol. C-39, pp. 269–272, 1990.
A. Antola, et al., “Fault tolerance in FFT arrays: time redundancy approaches,” J. VLSI Signal Processing, Vol. 4, pp. 295–316, 1992.
Y.-H. Choi and M. Malek, “A fault-tolerant FFT processor,” IEEE Trans. Compute., Vol. 37, No. 5, pp. 617–621, 1988.
J.-Y. Jou and J. A. Abraham, “Fault-tolerant FFT networks,” IEEE Trans. Compute., Vol. 37, No. 5, pp. 548–561, 1988.
M. Tsunoyama and S. Naito, “A fault-tolerant FFT processor,” Proc. 1991 IEEE Fault-Tolerant Computing Symp., pp. 128–135.
Y.-M. Hsu and E. E. Swartzlander, Jr., “Time redundant error correcting adders and multipliers,”Proc. 1992 IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 247–256.
Y.-M. Hsu and E. E. Swartzlander, Jr., “VLSI concurrent error correcting adders and multipliers,”Proc. 1993 IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 287–294.
Magic Tutorials, University of California, Berkeley, 1986.
Musa Manual, Sun Release 4.1, 1989.
The CAzM Users Manual, Research Triangle Park, NC: Microelectronics Center of North Carolina, 1989.
Y.-M. Hsu and E. E. Swartzlander, Jr., “Reliability estimation for time redundant error correcting adders and multipliers,” Proc. 1994 IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 159–167.
Y.-M. Hsu and E. E. Swartzlander, Jr., “Measuring delay time in adders using circuit simulations,” Proc. 37th Midwest Symp. Circuits and Systems, pp. 265–268, 1994.
Y.-M. Hsu and E. E. Swartzlander, Jr., “Sorting networks with built-in error correction,” Proc 1994 Int’l Conf Parall and Distr. Sys., pp. 379–384.
Y.-M. Hsu and E. E. Swartzlander, Jr., “FFT arrays with built-in error correction,” Proc. 28th Asilomar Conf Signals, Sys., and Compute 1994 pp. 172–176.
Y.-M. Hsu, V. Piuri, and E. E. Swartzlander, Jr., “Efficient dine redundancy for error correcting inner-product units and convolvers,” Proc. 1995 IEEE Int’l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 267–276.
Y.-M. Hsu, Concurrent Error Correcting Arithmetic Processors, Ph.D. Dissertation, Austin, TX: The University of Texas at Austin, 1995.
S. Al-Arian and M. Gumusel, “HPTR: hardware partition in time redundancy technique for fault tolerance,”Proc. 1992 IEEE SOUTHEASTCON, Vol. 2, pp. 630–633.
T. H. Chen, et al., “Design and analysis of VLSI-based arithmetic arrays with error correction,” Int’l J. Electronics, Vol. 72, No. 2, pp. 253–271, 1992.
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© 1997 Kluwer Academic Publishers
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Hsu, YM. (1997). Fault Tolerant Arithmetic. In: Swartzlander, E.E. (eds) Application Specific Processors. The Kluwer International Series in Engineering and Computer Science, vol 380. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1457-8_3
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DOI: https://doi.org/10.1007/978-1-4613-1457-8_3
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