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Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 380))

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Abstract

This chapter summarizes various techniques used to achieve fault tolerance in computer arithmetic. There are basically three approaches including hardware redundancy, information redundancy, and time redundancy. Hardware redundancy has the highest hardware overhead. However, its delay is minimal. In the information redundancy approach, both the hardware complexity and delay are higher than other approaches. Time redundancy uses the smallest amount of hardware at the expense of extra computation time. In this research a concurrent error correcting technique based on time redundancy called time shared TMR is developed. It has been successfully applied to ripple carry adders and array multipliers. VLSI ripple carry adders and array multipliers are designed. They are compared in area, delay and cycle time. The time shared TMR technique can also be applied to more complex arithmetic processors like sorting networks, FFT arrays, convolvers, and inner product units. This research is significant because the time shared TMR technique proves to be a high reliability, low hardware complexity, and reasonable delay penalty solution to fault tolerant arithmetic.

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© 1997 Kluwer Academic Publishers

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Hsu, YM. (1997). Fault Tolerant Arithmetic. In: Swartzlander, E.E. (eds) Application Specific Processors. The Kluwer International Series in Engineering and Computer Science, vol 380. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1457-8_3

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  • DOI: https://doi.org/10.1007/978-1-4613-1457-8_3

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8635-6

  • Online ISBN: 978-1-4613-1457-8

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