Abstract
The ever-increasing density of ASICs, the whole-sale switch to surface-mount technology, and the growing interest in multi-chip modules (MCM), have resulted in testable designs becoming a greater priority. Thus far, designers have considered testability as an issue which comes into play at the very end of the design cycle. However, in the ASIC design flow based on synthesis, it is essential that designers develop a test strategy and address testability issues concurrently with other activities in the design cycle. In this chapter, Test Synthesis and Automatic Test Pattern Generation (ATPG) using the Synopsys Test Compiler (TC) are discussed.
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References
Test Compiler Reference Manual
Test Compiler Streamlined Methodology Application Note
Synopsys Newsletter “Impact” Support Center Q&A
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© 1997 Kluwer Academic Publishers
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Kurup, P., Abbasi, T. (1997). Design for Testability. In: Logic Synthesis Using Synopsys®. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1455-4_8
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DOI: https://doi.org/10.1007/978-1-4613-1455-4_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8634-9
Online ISBN: 978-1-4613-1455-4
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